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ISL5629EVAL1 Scheda tecnica(PDF) 11 Page - Intersil Corporation |
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ISL5629EVAL1 Scheda tecnica(HTML) 11 Page - Intersil Corporation |
11 / 12 page 11 Propagation Delay The converter requires two clock rising edges for data to be represented at the output. Each rising edge of the clock captures the present data word and outputs the previous data. The propagation delay is therefore 1/CLK, plus <2ns of processing. See Figure 8. Test Service Intersil offers customer-specific testing of CommLink converters with a service called Testdrive. To submit a request, fill out the Testdrive form at www.intersil.com/testdrive. Or, send a request to the technical support center. RDIFF ISL5629 RLOAD FIGURE 6. OUTPUT LOADING FOR DATASHEET MEASUREMENTS OUTA OUTB VOUT = (2 x OUTA x REQ)V LOAD SEEN BY THE TRANSFORMER RLOAD REPRESENTS THE 1:1 REQ = 0.5 x (RLOAD // RDIFF) AT EACH OUTPUT FIGURE 7. ALTERNATIVE OUTPUT LOADING ISL5629 OUTA OUTB VOUT = (2 x OUTA x REQ)V REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB AT EACH OUTPUT RLOAD RDIFF RA RB LOAD SEEN BY THE TRANSFORMER RLOAD REPRESENTS THE Timing Diagram FIGURE 8. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM CLK IOUT 50% tPW1 tPW2 tSU tHLD tSU tSU tPD tHLD tHLD D7-D0 W0 W1 W2 W3 OUTPUT=W0 OUTPUT=W1 tPD OUTPUT=W-1 ISL5629 |
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Descrizione simile - ISL5629EVAL1 |
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