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ADMC300 Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADMC300 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 42 page –4– REV. B ADMC300–SPECIFICATIONS ENCODER INTERFACE UNIT Parameter Test Conditions Min Typ Max Unit fENC, MAX Maximum Encoder Pulse Rate1 3.1 MHz NOTES 1Assumes perfect quadrature encoder signals. Specifications subject to change without notice. AUXILIARY PWM OUTPUTS Parameter Test Conditions Min Typ Max Unit Resolution 8 Bits fAUXPWM Switching Frequency 48.8 kHz Specifications subject to change without notice. (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40 C to +85 C, CLKIN = 12.5 MHz, unless otherwise noted) (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40 C to +85 C, CLKIN = 12.5 MHz, unless otherwise noted) TIMING PARAMETERS Parameter Min Max Unit Clock Signals tCK is defined as 0.5 tCKI. The ADMC300 uses an input clock with a frequency equal to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns) yields a 40 ns processor cycle (equivalent to 25 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain specification value. Example: tCKH = 0.5 tCK – 10 ns = 0.5 (40 ns) – 10 ns = 10 ns. Timing Requirements: tCKI CLKIN Period 80 150 ns tCKIL CLKIN Width Low 20 ns tCKIH CLKIN Width High 20 ns Switching Characteristics: tCKL CLKOUT Width Low 0.5 tCK – 10 ns tCKH CLKOUT Width High 0.5 tCK – 10 ns tCKOH CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement: tRSP RESET Width Low 5 tCK 1 ns PWM Shutdown Signals Timing Requirements: tPWMTPW PWMTRIP Width Low 3 tCK ns tPIOPWM PIO Width Low 3 tCK ns NOTES 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). Specifications subject to change without notice. CLKIN CLKOUT tCKOH tCKI tCKIH tCKH tCKL tCKIL Figure 1. Clock Signals |
Codice articolo simile - ADMC300_15 |
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Descrizione simile - ADMC300_15 |
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