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AD8230 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD8230 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 16 page AD8230 Rev. B | Page 11 of 16 THEORY OF OPERATION Auto-zeroing is a dynamic offset and drift cancellation technique that reduces input-referred voltage offset to the μV level and voltage offset drift to the nV/°C level. A further advantage of dynamic offset cancellation is the reduction of low frequency noise, in particular the 1/f component. The AD8230 is an instrumentation amplifier that uses an auto-zeroing topology and combines it with high common- mode signal rejection. The internal signal path consists of an active differential sample-and-hold stage (preamp) followed by a differential amplifier (gain amp). Both amplifiers implement auto-zeroing to minimize offset and drift. A fully differential topology increases the immunity of the signals to parasitic noise and temperature effects. Amplifier gain is set by two external resistors for convenient TC matching. The signal sampling rate is controlled by an on-chip, 6 kHz oscillator and logic to derive the required nonoverlapping clock phases. For simplification of the functional description, two sequential clock phases, A and B, are shown to distinguish the order of internal operation, as depicted in Figure 30 and Figure 31, respectively. – – + + VREF CHOLD VOUT V+IN V–IN CHOLD CSAMPLE RF RG PREAMP GAIN AMP VDIFF +VCM –VS –VS Figure 30. Phase A of the Sampling Phase During Phase A, the sampling capacitors are connected to the inputs. The input signal’s difference voltage, VDIFF, is stored across the sampling capacitors, CSAMPLE. Because the sampling capacitors only retain the difference voltage, the common-mode voltage is rejected. During this period, the gain amplifier is not connected to the preamplifier so its output remains at the level set by the previously sampled input signal held on CHOLD, as shown in Figure 30. – – + + VREF CHOLD VOUT V+IN V–IN CHOLD CSAMPLE RF RG PREAMP GAIN AMP VDIFF +VCM –VS –VS Figure 31. Phase B of the Sampling Phase In Phase B, the differential signal is transferred to the hold capacitors refreshing the value stored on CHOLD. The output of the preamplifier is held at a common-mode voltage determined by the reference potential, VREF. In this manner, the AD8230 is able to condition the difference signal and set the output voltage level. The gain amplifier conditions the updated signal stored on the hold capacitors, CHOLD. SETTING THE GAIN Two external resistors set the gain of the AD8230. The gain is expressed in the following equation: ) 2(1 G F R R Gain + = (1) 2 6 1 7 5 8 4 3 AD8230 VOUT –VS +VS 0.1µF RG RF RG VREF1 VREF2 0.1µF 10µF 10µF Figure 32. Gain Setting Table 5. Gains Using Standard 1% Resistors Gain RF RG Actual Gain 2 0 Ω (short) None 2 10 8.06 kΩ 2 kΩ 10 50 12.1 kΩ 499 Ω 50.5 100 9.76 kΩ 200 Ω 99.6 200 10 kΩ 100 Ω 202 500 49.9 kΩ 200 Ω 501 1000 100 kΩ 200 Ω 1002 Figure 32 and Table 5 provide an example of some gain settings. As Table 5 shows, the AD8230 accepts a wide range of resistor values. Because the instrumentation amplifier has finite driving capability, ensure that the output load in parallel with the sum of the gain setting resistors is greater than 2 kΩ. RL ||(RF + RG) > 2 kΩ (2) Offset voltage drift at high temperature can be minimized by keeping the value of the feedback resistor, RF, small. This is due to the junction leakage current on the RG pin, Pin 7. The effect of the gain setting resistor on offset voltage drift is shown in Figure 33. In addition, experience has shown that wire-wound resistors in the gain feedback loop may degrade the offset voltage performance. |
Codice articolo simile - AD8230_15 |
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Descrizione simile - AD8230_15 |
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