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AD8177 Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD8177 Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 40 page AD8177 Rev. 0 | Page 6 of 40 TIMING CHARACTERISTICS (PARALLEL MODE) Table 7. Limit Parameter Symbol Min Typ Max Unit Parallel Data Setup Time t1 80 ns WE Pulse Width t2 110 ns Parallel Hold Time t3 150 ns WE Pulse Separation t4 90 ns WE to UPDATE Delay t5 10 ns UPDATE Pulse Width t6 90 ns Propagation Delay, UPDATE to Switch On 80 ns RST Time 140 200 ns t2 t4 1 0 WE 1 0 t1 t3 1 = LATCHED 0 = TRANSPARENT UPDATE t6 D0 TO D4 A0 TO A2 t5 Figure 3. Timing Diagram, Parallel Mode Table 8. Logic Levels, VDD = 3.3 V VIH VIL VOH VOL IIH IIL IOH IOL SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, UPDATE SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, UPDATE SEROUT SEROUT SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, UPDATE SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, UPDATE SEROUT SEROUT 2.0 V min 0.6 V max Disabled Disabled 20 μA max −20 μA max Disabled Disabled Table 9. H and V Logic Levels, VDD = 3.3 V VOH VOL IOH IOL 2.7 V min 0.5 V max –3 mA max 3 mA max Table 10. RST Logic Levels, VDD = 3.3 V VIH VIL IIH IIL 2.0 V min 0.6 V max −60 μA max −120 μA max Table 11. CS Logic Levels, VDD = 3.3 V VOH VOL IIH IOL 2.0 V min 0.6 V max 100 μA max 40 μA max |
Codice articolo simile - AD8177_15 |
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Descrizione simile - AD8177_15 |
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