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CD4527BMS Scheda tecnica(PDF) 1 Page - Intersil Corporation |
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CD4527BMS Scheda tecnica(HTML) 1 Page - Intersil Corporation |
1 / 11 page 7-1216 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4527BMS CMOS BCD Rate Multiplier Features • High Voltage Type (20V Rating) • Cascadable in Multiples of 4-Bits • Set to “9” Input and “9” Detect Output • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Numerical Control • Instrumentation • Digital Filtering • Frequency Synthesis December 1992 File Number 3343 Description CD4527BMS is a low power 4-bit digital rate multiplier that provides an output pulse rate which is the clock input pulse rate multiplied by 1/10 times the BCD input. For example, when the BCD input is 8, there will be 8 output pulses for every 10 input pulses. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversion, and frequency division. For fractional multipliers with more than one digit, CD4527BMS devices may be cascaded in two different modes: the Add mode and the Multiply mode (see Figures 9 and 11). In the Add mode, In the Multiply mode, the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second one, pulses for every 100 clock input pulses. The CD4527BMS is supplied in these 16-lead outline packages: Output Rate = (Clock Rate) [0.1BCD1 + 0.01BCD2 + 0.001BCD3 + . . .] e.g. 9 x 4 = 36 or 36 output 10 10 100 Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W Pinout CD4527BMS TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 “9” OUT C D SET TO “9” OUT OUT VSS INHIBIT OUT (CARRY) VDD A CLEAR CASCADE INHIBIT IN (CARRY) STROBE CLOCK B Functional Diagram VSS = 8 VDD = 16 RATE A SELECT LOGIC 14 B 15 C 2 D 3 STROBE 10 CASCADE 12 BCD RATE SELECT INPUTS 6 5 OUT OUT RATE OUTPUTS INHIBIT (CARRY) IN 11 4 13 CLEAR SET TO NINE INHIBIT (CARRY) OUT “9” OUT 1 7 CLOCK 9 ÷10 COUNTER |
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