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CD4099BMS Scheda tecnica(PDF) 6 Page - Intersil Corporation |
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CD4099BMS Scheda tecnica(HTML) 6 Page - Intersil Corporation |
6 / 10 page 7-499 Specifications CD4099BMS Logic Diagram TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD 9V ± -0.5V OSCILLATOR 50kHz 25kHz Static Burn-In 1 Note 1 1, 9-15 2-8 16 Static Burn-In 2 Note 1 1, 9-15 8 2-7, 16 Dynamic Burn- In Note 1 - 5-8 16 1, 9-15 2, 4 3 Irradiation Note 2 1, 9-15 8 2-7, 16 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V A0 A1 A2 LATCH 0 D WD R 9 Q0 A0 A1 A2 LATCH 1 D WD R 10 Q1 A0 A1 A2 LATCH 2 D WD R 11 Q2 A0 A1 A2 LATCH 3 D WD R 12 Q3 A0 A1 A2 LATCH 4 D WD R 13 Q4 A0 A1 A2 LATCH 5 D WD R 14 Q5 A0 A1 A2 LATCH 6 D WD R 15 Q6 A0 A1 A2 LATCH 7 D WD R 1 Q7 A0 A0 A0 5 * A1 A1 A1 6 * A2 A2 A2 7 * D DATA 3 * WD WRITE DISABLE 4 * R RESET 2 * VSS = 8 VDD = 16 R ADDRESS WD DATA p n p n Q VDD VSS *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK |
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