Motore di ricerca datesheet componenti elettronici |
|
CD4095BMS Scheda tecnica(PDF) 1 Page - Intersil Corporation |
|
CD4095BMS Scheda tecnica(HTML) 1 Page - Intersil Corporation |
1 / 10 page 7-1094 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4095BMS CD4096BMS CMOS Gated J-K Master-Slave Flip-Flops Features • Set-Reset Capability • High Voltage Types (20V Rating) • CD4095BMS Non-Inverting J and K Inputs • CD4096BMS Inverting and Non-Inverting J and K Inputs • 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V • Gated Inputs • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Registers • Counters • Control Circuits Description CD4095BMS and CD4096BMS are J-K Master-Slave Flip- Flops featuring separate AND gating of multiple J and K inputs. The gated J-K inputs control transfer of information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation. The CD4095BMS and CD4096BMS are supplied in these 14 lead outline packages: Braze Seal DIP H4Q Frit Seal DIP H1A File Number 3331 Pinouts CD4095BMS TOP VIEW CD4096BMS TOP VIEW Functional Diagrams CD4095BMS CD4096BMS NC RESET J1 J2 J3 Q VSS VDD SET CLOCK K1 K2 K3 Q 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC RESET J1 J2 J3 Q VSS VDD SET CLOCK K1 K2 K3 Q 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC = NO CONNECTION VDD = 14 VSS = 7 SET J2 J3 13 3 5 4 J1 K2 K3 11 9 10 K1 12 CLOCK S JQ CL K R Q Q Q RESET 2 NC = 1 6 8 VDD = 14 VSS = 7 SET J2 J3 13 3 5 4 J1 K2 K3 11 9 10 K1 12 CLOCK S JQ CL K R Q Q Q RESET 2 NC = 1 6 8 December 1992 |
Codice articolo simile - CD4095BMS |
|
Descrizione simile - CD4095BMS |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |