AD7777_15 datasheet(2/12 Pages) AD

Il numero della parte	AD7777

Spiegazioni elettronici	LC MOS High Speed 1. 4 and 8 Channel 10 Bit ADCs

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Produttore elettronici	AD [Analog Devices]

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REV. A

–2–

AD7776/AD7777/AD7778–SPECIFICATIONS

CLKIN = 8 MHz; RTN = O V; CREFIN = 10 nF; all specifications TMIN to TMAX unless otherwise noted.)

Parameter

A Versions

1

Units

Conditions/Comments

DC ACCURACY

Resolution

2

10

Bits

Relative Accuracy

±1

LSB max

See Terminology

Differential Nonlinearity

±1

LSB max

No Missing Codes; See Terminology

Bias Offset Error

±12

LSB max

See Terminology

Bias Offset Error Match

10

LSB max

Between Channels, AD7777/AD7778 Only; See Terminology

Plus or Minus Full-Scale Error

±12

LSB max

See Terminology

Plus or Minus Full-Scale Error Match 10

LSB max

Between Channels, AD7777/AD7778 Only; See Terminology

ANALOG INPUTS

Input Voltage Range

All Inputs

VBIAS

± V

SWING

V min/V max

Input Current

+200

µA max

VIN = VBIAS

± V

SWING; Any Channel

REFERENCE INPUT

REFIN

1.9/2.1

V min/V max

For Specified Performance

REFIN Input Current

+200

µA max

REFERENCE OUTPUT

REFOUT

1.9/2.1

V min/V max

Nominal REFOUT = 2.0 V

DC Output Impedance

5

Ω typ

Reference Load Change

±2

mV max

For Reference Load Current Change of 0 to

±500 µA

±5

mV max

For Reference Load Current Change of 0 to

±1 mA

Reference Load Should Not Change During Conversion

Short Circuit Current

3

20

mA max

See Terminology

LOGIC OUTPUTS

DB0–DB9,

BUSY/INT

VOL, Output Low Voltage

0.4

V max

ISINK = 1.6 mA

VOH, Output High Voltage

4.0

V min

ISOURCE = 200

µA

Floating State Leakage Current

±10

µA max

Floating State Capacitance

3

10

pF max

ADC Output Coding

Twos Complement

LOGIC INPUTS

DB0–DB9,

CS, WR, RD, CLKIN

Input Low Voltage, VINL

0.8

V max

Input High Voltage, VINH

2.4

V min

Input Leakage Current

10

µA max

Input Capacitance

3

10

pF max

CONVERSION TIMING

Acquisition Time

4.5 tCLKIN

ns min

See Terminology

5.5 tCLKIN + 70

ns max

Single Conversion

14 tCLKIN

ns max

Double Conversion

28 tCLKIN

ns max

tCLKIN

125/500

ns min/ns max Period of Input Clock CLKIN

tCLKIN High

50

ns min

Minimum High Time for CLKIN

tCLKIN Low

40

ns min

Minimum Low Time for CLKIN

POWER REQUIREMENTS

VCC Range

4.75/5.25

V min/V max

For Specified Performance

ICC, Normal Mode

15

mA max

CS = RD = +5 V, CR8 = 0

ICC, Power-Down Mode

1.5

mA max

CR8 = 1. All Linear Circuitry OFF

Power-Up Time to Operational

Specifications

500

µs max

From Power-Down Mode

DYNAMIC PERFORMANCE

See Terminology

Signal to Noise and Distortion

S/(N+D) Ratio

–56

dB min

VIN = 99.88 kHz Full-Scale Sine Wave with fSAMPLING = 380.95 kHz

Total Harmonic Distortion (THD)

–60

dB min

VIN = 99.88 kHz Full-Scale Sine Wave with fSAMPLING = 380.95 kHz

Intermodulation Distortion (IMD)

–75

dB typ

fa = 103.2 kHz, fb = 96.5 kHz with fSAMPLING = 380.95 kHz. Both

Signals Are Sine Waves at Half-Scale Amplitude

Channel-to-Channel Isolation

–90

dB typ

VIN = 100 kHz Full-Scale Sine Wave with fSAMPLING = 380.95 kHz

NOTES

1Temperature range as follows: A = –40

°C to +85°C.

21 LSB = (2

× V

SWING)/1024 = 1.95 mV for VSWING = 1.0 V.

3Guaranteed by design, not production tested.

Specifications subject to change without notice.

(VCC = +5 V

5%; AGND = DGND = O V;

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