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AD7732 Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte AD7732
Spiegazioni elettronici  2-Channel, 10 V Input Range, High Throughput, 24-Bit ADC
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7732 Scheda tecnica(HTML) 6 Page - Analog Devices

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AD7732
Rev. A | Page 6 of 32
TIMING SPECIFICATIONS
Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise
noted.)1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Master Clock Range
1
6.144
MHz
t1
50
ns
SYNC Pulsewidth
t2
500
ns
RESET Pulsewidth
Read Operation
t4
0
ns
CS Falling Edge to SCLK Falling Edge Setup Time
t52
SCLK Falling Edge to Data Valid Delay
0
60
ns
DVDD of 4.75 V to 5.25 V
0
80
ns
DVDD of 2.7 V to 3.3 V
t5A2, 3
CS Falling Edge to Data Valid Delay
0
60
ns
DVDD of 4.75 V to 5.25 V
0
80
ns
DVDD of 2.7 V to 3.3 V
t6
50
ns
SCLK High Pulsewidth
t7
50
ns
SCLK Low Pulsewidth
t8
0
ns
CS Rising Edge after SCLK Rising Edge Hold Time
t94
10
80
ns
Bus Relinquish Time after SCLK Rising Edge
Write Operation
t11
0
ns
CS Falling Edge to SCLK Falling Edge Setup
t12
30
ns
Data Valid to SCLK Rising Edge Setup Time
t13
25
ns
Data Valid after SCLK Rising Edge Hold Time
t14
50
ns
SCLK High Pulsewidth
t15
50
ns
SCLK Low Pulsewidth
t16
0
ns
CS Rising Edge after SCLK Rising Edge Hold Time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of
1.6 V. See Figure 2 and Figure 3.
2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits.
3 This specification is relevant only if CS goes low while SCLK is low.
4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.


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