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CA3282 Scheda tecnica(PDF) 5 Page - Intersil Corporation |
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CA3282 Scheda tecnica(HTML) 5 Page - Intersil Corporation |
5 / 10 page 5 sensed by an out of saturation condition. A high on CE forces MISO to a high impedance state. Also, when CE is high, the octal driver ignores the SCK and MOSI signals. SCK, MISO, MOSI - See Serial Peripheral Interface (SPI) section in this data sheet. VDD and VSS (GND) - Positive and negative power supply lines. Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) utilized by the CA3282 is a serial synchronous bus for control and data transfers. The Clock (SCK), which is generated by the microcomputer, is active only during data transfers. In systems using CDP68HC05 family microcomputers, the inactive clock polarity is determined by the CPOL bit in the microcom- puter’s control register. The CPOL bit is used in conjunction with the clock phase bit, CPHA to produce the desired clock data relationship between the microcomputer and octal driver. The CPHA bit in general selects the clock edge which captures data and allows it to change states. For the CA3282, the CPOL bit must be set to a logic zero and the CPHA bit to a logic one. Configured in this manner, MISO (output) data will appear with every rising edge SCK, and MOSI (input) data will be latched into the shift register with every falling edge of SCK. Also, the steady state value of the inactive serial clock, SCK, will be at a low level. Timing dia- grams for the serial peripheral interface are shown in Figure 1. SPI Signal Descriptions MOSI (Master Out/Slave In) - Serial data input. Data bytes are shifted in at this pin, most significant bit (MSB) first. The data is passed directly to the shift register which in turn con- trols the latches and output drivers. A logic “0” on this pin will program the corresponding output to be ON, and a logic “1” will turn it OFF. MISO (Master In/Slave Out) - Serial data output. Data bytes are shifted out at this pin, most significant bit (MSB) first. This pin is the serial output from the shift register and is three stated when CE is high. A high for a data bit on this pin indicates that the corresponding output is high. A low on this pin for a data bit indicates that the output is low. Comparing the serial output bits with the previous input bits, the micro- computer implements the diagnostic data supplied by the CA3282. SCK - Serial clock input. This signal clocks the shift register SCK and new MOSI (input) data will be latched into the shift register on every falling edge of SCK. The SCK phase bit, CPHA, and polarity bit, CPOL, must be set to 1 and 0, respectively in the microcomputer’s control register. Functional Descriptions The CA3282 is a low operating power, high voltage, high cur- rent, octal power driver featuring eight channels of open drain NDMOS output drivers. The drivers have low satura- tion voltage and output short circuit protection, suited for driving resistive or inductive loads such as lamps, relays and solenoids. Data is transmitted to the device serially using the Serial Peripheral Interface (SPI) protocol. Each channel is independently controlled by an output latch and a common RESET line that disables all eight outputs. Byte timing with asynchronous reset is shown in Figure 4. The circuit receives 8-bit serial data by means of the serial input (MOSI), and stores this data in an internal register to control the output drivers. The serial output (MISO) provides 8-bit diagnostic data representing the voltage level at the driver output. This allows the microcomputer to diagnose the con- dition at the output drivers. The device is selected when the chip enable (CE) line is low. When (CE) is high, the device is deselected and the serial output (MISO) is placed in a three- state mode. The device shifts serial data on the rising edge of the serial clock (SCK), and latches data on the falling edge. On the rising edge of chip enable (CE), new input data from the shift register is latched in the output drivers. The falling edge of chip enable (CE) transfers the output drivers fault information back to the shift register. The output drivers have low ON voltage at rated current, and are monitored by a comparator for an out of saturation condition, in which case the output driver with the fault becomes unlatched and diagnostic data is sent to the microcomputer via the MISO line. A typical microcomputer interface circuit is shown in Figure 2. Also, the CA3282 may be cascaded with another CA3282 octal driver. Shift Register The shift register has both serial and parallel inputs and out- puts. Serial output and input data are simultaneously trans- ferred to and from the SPI bus. The parallel outputs are latched into the output latch in the CA3282 at the end of a data transfer. The parallel inputs jam diagnostic data into the shift register at the beginning of a data transfer cycle. Output Latch The output latch holds input data from the shift register which is used to activate the outputs. The latch circuit may be cleared by a fault condition (to protect the overloaded out- puts), or by the RESET signal. PORT MOSI MISO SCK MOSI MISO SCK RESET CDP68HC05C4 MICROCOMPUTER CA3282 FIGURE 3. TYPICAL MICROCOMPUTER INTERFACE WITH THE CA3282 CE RESET CA3282 |
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