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AD7523JN Scheda tecnica(PDF) 7 Page - Intersil Corporation |
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AD7523JN Scheda tecnica(HTML) 7 Page - Intersil Corporation |
7 / 9 page 10-14 Offset Adjustment 1. Adjust VREF to approximately +10V. 2. Connect all digital inputs to “Logic 1”. 3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at IOUT2 amplifier output. 4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. 5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at VOUT. Gain Adjustment 1. Connect all digital inputs to V+. 2. Monitor VOUT for a -VREF (1 - 2 -9) volts reading. 3. To increase VOUT, connect a series resistor of up to 250Ω between VOUT and RFEEDBACK. 4. To decrease VOUT, connect a series resistor of up to 250Ω between the reference voltage and the VREF terminal. FIGURE 5. PROGRAMMABLE FUNCTION GENERATOR VOUT = -VIN/D Where: FIGURE 6. DIVIDER (DIGITALLY CONTROLLED GAIN) FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET 6 - + OUT1 15 16 1 4 13 3 2 AD7523/ MSB LSB 14 NC DIGITAL FREQUENCY CONTROL WORD AD7533 +15V VDD A1 C1 CALIBRATE 10K 6.8V (2) 6 - + A2 10K 1% 10K 1% 4.7K TRIANGULAR WAVE SQUARE WAVE 1K OUT2 6 - + OUT2 14 24 11 3 1 AD7523/ MSB LSB 16 +15V VIN DIGITAL INPUT AD7533 15 BIT 8 (10) (AD7533) BIT 1 “D” VREF VOUT OUT1 RFB D Bit 1 2 1 ------------- Bit 2 2 2 ------------- …Bit 8 2 2 ------------- ++ = 0D 255 256 ---------- ≤≤ 6 - + 15 16 1 4 13 3 2 AD7523/ MSB LSB 14 R1 AD7533 +15V 6 - + BIT 1 BIT 8 DIGITAL INPUT “D” R2 VREF VOUT (10) (AD7533) V OUT V REF R 2 R 1 R 2 + ---------------------- R 1 D R 1 R 2 + ---------------------- – = Where D Bit 1 2 1 ------------ Bit 2 2 2 ------------ …Bit 8 2 8 ------------ ++ = 0D 255 256 ---------- ≤≤ AD7523, AD7533 |
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