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Motore di ricerca datesheet componenti elettronici |
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ISL54233IRTZ Scheda tecnica(PDF) 10 Page - Intersil Corporation |
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ISL54233IRTZ Scheda tecnica(HTML) 10 Page - Intersil Corporation |
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10 / 18 page  ISL54233 10 FN7918.0 December 21, 2011 BOARD LAYOUT GUIDELINES • The ISL54233 device must be soldered directly onto the PCB board. No IC sockets can be used. Their parasitic impedance will degrade the frequency performance. • The signal traces (1D+, 1D-, 2D+, 2D-, 3D+, 3D-, COM- and COM+) must have a controlled (characteristic) impedance of 50Ω ±5% . Tight control on trace width and dielectric thickness must be followed to get 50Ω lines. Impedance tests results for controlled lines should be requested from the board fabrication house. • A four layer PCB board: Signal (top) layer), Thin-Dielectric, GND (2nd layer), Thick-Dielectric, GND (3rd layer), Thin-Dielectric, Signal (Bottom layer) is required to achieve 50Ω traces. The top and bottom thin-dielectric are Nelco 4000-13 or Rogers 4350 core type material. The center thick-dielectric is FR4 pre-preg material. Figure 10 illustrates the material and sequencing of the layers. The dimensions called out are those required to achieve 50Ω microstrip for the signal traces. • Route all controlled impedance signal lines on the top (signal) layer with no vias or through holes. Vias or through holes make it difficult to maintain a controlled impedance and tend to generate reflections. • The signal trace lengths should be as short ( <1 inch from SMA connector to the switch pin) and straight as possible. If it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal by minimizing impedance discontinuities. • Use Edge - Launch SMA connectors for all signal lines. The SMA connector terminal should be tapered to the signal trace. • Ground stitching should be done along signal traces and around SMA ground connectors. This helps to isolate the trace in a ground conduit. This reduces capacitive coupling between traces and provides a good return path for the signal. • Use dry film solder mask. Clear the solder mask from signal trace. • Power and/or logic lines can be run on the bottom layer. Logic lines should be routed away from the signal lines. This will minimize capacitive coupling from the logic lines. • A 4.7µF capacitor is placed from VCC to GND where the power is brought onto the board. It keeps any low frequency noise from getting on the board. Since a bulk capacitor will look inductive at higher frequencies, an additional 0.1µF capacitor is placed across the supply lines. A 0.01µF decoupling capacitor needs to be connected from the VDD pin to ground of the ISL54233 part to filter out any power supply noise from entering the part. The capacitor should be a RF type chip capacitor and should be located as close to the VDD pin as possible. Note: RF type capacitors have a smaller foot-print than regular capacitors. FIGURE 10. FOUR LAYER BOARD STACK-UP TOP (SIGNAL) LAYER GND LAYER FR4 PRE-PREG GND LAYER BOTTOM LAYER 5 mil 52 mil 5 mil 10 mil ROGERS 4350 CORE ROGERS 4350 CORE TRACE GND GND |
Codice articolo simile - ISL54233IRTZ |
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Descrizione simile - ISL54233IRTZ |
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