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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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CD82C54-12 Scheda tecnica(PDF) 10 Page - Intersil Corporation |
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CD82C54-12 Scheda tecnica(HTML) 10 Page - Intersil Corporation |
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10 / 17 page  4-10 Mode 3: Square Wave Mode Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N CLK cycles. GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low while OUT is low, OUT is set high immedi- ately; no CLK pulse is required. A trigger reloads the Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to synchronize the Counter. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the cur- rent counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current half-cycle. FIGURE 12. MODE 3 Mode 3 is Implemented as Follows: EVEN COUNTS: OUT is initially high. The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses. When the count expires, OUT changes value and the Counter is reloaded with the initial count. The above process is repeated indefinitely. ODD COUNTS: OUT is initially high. The initial count is loaded on one CLK pulse, decremented by one on the next CLK pulse, and then decremented by two on succeeding CLK pulses. When the count expires, OUT goes low and the Counter is reloaded with the initial count. The count is decremented by three on the next CLK pulse, and then by two on succeeding CLK pulses. When the count expires, OUT goes high again and the Counter is reloaded with the initial count. The above pro- cess is repeated indefinitely. So for odd counts, OUT will be high for (N + 1)/2 counts and low for (N - 1)/2 counts. Mode 4: Software Triggered Mode OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse then go high again. The count- ing sequence is “Triggered” by writing the initial count. GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This CLK pulse does not decre- ment the count, so for an initial count of N, OUT does not strobe low until N + 1 CLK pulses after the initial count is written. If a new count is written during counting, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: (1) Writing the first byte has no effect on counting. (2) Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the sequence to be “retriggered” by software. OUT strobes low N + 1 CLK pulses after the new count of N is written. NN N N 0 2 0 4 0 2 0 4 0 2 0 4 0 2 0 4 0 4 0 2 NN N N 0 4 0 2 0 5 0 2 0 5 0 4 0 2 0 5 0 5 0 2 NN N N 0 2 0 4 0 2 0 2 0 2 0 4 0 2 0 4 0 4 0 2 WR CLK GATE OUT CW = 16 LSB = 4 WR CLK GATE OUT WR CLK GATE OUT CW = 16 LSB = 5 CW = 16 LSB = 4 82C54 |
Codice articolo simile - CD82C54-12 |
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Descrizione simile - CD82C54-12 |
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