Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

CS82C37A Scheda tecnica(PDF) 3 Page - Intersil Corporation

Il numero della parte CS82C37A
Spiegazioni elettronici  CMOS High Performance Programmable DMA Controller
Download  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CS82C37A Scheda tecnica(HTML) 3 Page - Intersil Corporation

  CS82C37A Datasheet HTML 1Page - Intersil Corporation CS82C37A Datasheet HTML 2Page - Intersil Corporation CS82C37A Datasheet HTML 3Page - Intersil Corporation CS82C37A Datasheet HTML 4Page - Intersil Corporation CS82C37A Datasheet HTML 5Page - Intersil Corporation CS82C37A Datasheet HTML 6Page - Intersil Corporation CS82C37A Datasheet HTML 7Page - Intersil Corporation CS82C37A Datasheet HTML 8Page - Intersil Corporation CS82C37A Datasheet HTML 9Page - Intersil Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 23 page
background image
4-194
82C37A
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
VCC
31
VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for
decoupling.
GND
20
Ground
CLK
12
I
CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A
operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for
the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for
standby operation.
CS
11
I
CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET
13
I
RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.
READY
6
I
READY: This signal can be used to extend the memory read and write pulses from the 82C37A to
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.
HLDA
7
I
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of CLK, during which time HLDA must not transition.
DREQ0-
DREQ3
16-19
I
DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.
DB0-DB7
21-23
26-30
I/O
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write
the data into the new memory location.
IOR
1
I/O
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.
IOW
2
I/O
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output
control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.


Codice articolo simile - CS82C37A

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Harris Corporation
CS82C37A HARRIS-CS82C37A Datasheet
204Kb / 23P
   CMOS High Performance Programmable DMA Controller
logo
Intersil Corporation
CS82C37A INTERSIL-CS82C37A Datasheet
427Kb / 24P
   CMOS High Performance Programmable DMA Controller
logo
Harris Corporation
CS82C37A-12 HARRIS-CS82C37A-12 Datasheet
204Kb / 23P
   CMOS High Performance Programmable DMA Controller
logo
Intersil Corporation
CS82C37A-12 INTERSIL-CS82C37A-12 Datasheet
427Kb / 24P
   CMOS High Performance Programmable DMA Controller
CS82C37A-1296 INTERSIL-CS82C37A-1296 Datasheet
427Kb / 24P
   CMOS High Performance Programmable DMA Controller
More results

Descrizione simile - CS82C37A

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Harris Corporation
82C37 HARRIS-82C37 Datasheet
204Kb / 23P
   CMOS High Performance Programmable DMA Controller
logo
Intersil Corporation
82C37A INTERSIL-82C37A_06 Datasheet
427Kb / 24P
   CMOS High Performance Programmable DMA Controller
82C237 INTERSIL-82C237 Datasheet
158Kb / 25P
   CMOS High Performance Programmable DMA Controller
March 1997
HS-82C37ARH INTERSIL-HS-82C37ARH_00 Datasheet
268Kb / 21P
   Radiation Hardened CMOS High Performance Programmable DMA Controller
logo
NEC
UPD8237A NEC-UPD8237A Datasheet
973Kb / 17P
   HIGH-PERFORMANCE PROGRAMMABLE DMA CONTROLLER
logo
Intersil Corporation
HS-82C37ARH INTERSIL-HS-82C37ARH Datasheet
195Kb / 29P
   Radiation Hardened CMOS High Performance Programmable DMA Controller
logo
Harris Corporation
HS-82C37 HARRIS-HS-82C37 Datasheet
253Kb / 28P
   Radiation Hardened CMOS High Performance Programmable DMA Controller
logo
NEC
UPD8257 NEC-UPD8257 Datasheet
608Kb / 11P
   PROGRAMMABLE DMA CONTROLLER
logo
Intel Corporation
M8257 INTEL-M8257 Datasheet
360Kb / 7P
   PROGRAMMABLE DMA CONTROLLER
logo
Advanced Micro Devices
AM8257 AMD-AM8257 Datasheet
519Kb / 8P
   Programmable DMA Controller
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com