AD6622_15 datasheet(4/28 Pages) AD

Il numero della parte	AD6622

Spiegazioni elettronici	Four-Channel, 75 MSPS Digital Transmit Signal Processor

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Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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AD6622

–4–

REV. 0

Test

AD6622AS

Name

Parameter (Conditions)

Temp

Level

Min

Typ

Max

Unit

MICROPROCESSOR PORT, MODE MNM (MODE = 1)

MODE MNM Write Timing:

tHDS

DS(RD) to DTACK(RDY) Hold Time

Full

IV

0

ns

tHRW

R/

W(WR) to DTACK(RDY) Hold Time

Full

IV

0

ns

tSAM

Address/Data to R/

W(WR) Setup Time

Full

IV

0

ns

tHAM

Address/Data to R/

W(WR) Hold Time

Full

IV

0

ns

tDDTACK

DS(RD) to DTACK(RDY) Delay

Full

IV

1

× tCLK

ns

tACCFAST

R/

W(WR) to DTACK(RDY) Low Delay

Full

IV

2

× t

CLK

3

× t

CLK

ns

tACCMEDIUM

R/

W(WR) to DTACK(RDY) Low Delay

Full

IV

3

× tCLK

4

× tCLK

ns

tACCSLOW

R/

W(WR) to DTACK(RDY) Low Delay

Full

IV

4

× tCLK

5

× tCLK

ns

MODE MNM Read Timing:

tSAM

Address to

DS(RD) Setup Time

Full

IV

0

ns

tHA

Address to Data Hold Time

Full

IV

0

ns

tZD

Data Three-State Delay

Full

IV

0

ns

tDD

DTACK(RDY) to Data Delay

Full

IV

tCLK – 10

ns

tDDTACK

DS(RD) to DTACK(RDY) Delay

Full

IV

1

× t

CLK

ns

tACCFAST

DS(RD) to DTACK(RDY) Low Delay

Full

IV

2

× tCLK

3

× tCLK

ns

tACCMEDIUM

DS(RD) to DTACK(RDY) Low Delay

Full

IV

3

× tCLK

4

× tCLK

ns

tACCSLOW

DS(RD) to DTACK(RDY) Low Delay

Full

IV

4

× t

CLK

5

× t

CLK

ns

NOTES

1All Timing Speciﬁcations valid over VDD range of 2.4 V to 3.3 V.

Speciﬁcations subject to change without notice.

CLK

OUT[17:0],

QOUT

tCLK

tCLKL

tCLKH

tZO

tHO

tZO

OEN

tSO

Figure 1. Parallel Output Switching Characteristics

CLK

SCLK

SDFS

SDI

CLKn

DATAn

tDSCLK

tDSDFS

tSSI

tHSI

Figure 2. Serial Port Switching Characteristics

CLK

IN[17:0],

QIN

tSI

tHI

Figure 3. Wideband Input Timing

SYNC

CLK

tSS

tHS

Figure 4. SYNC Timing Inputs

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