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CS80C88-2 Scheda tecnica(PDF) 10 Page - Intersil Corporation |
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CS80C88-2 Scheda tecnica(HTML) 10 Page - Intersil Corporation |
10 / 32 page 3-10 Bus Operation The 80C88 address/data bus is broken into three parts: the lower eight address/data bits (AD0-AD7), the middle eight address bits (A8-A15), and the upper four address bits (A16- A19). The address/data bits and the highest four address bits are time multiplexed. This technique provides the most efficient use of pins on the processor, permitting the use of standard 40 lead package. The middle eight address bits are not multiplexed, i.e., they remain valid throughout each bus cycle. In addition, the bus can be demultiplexed at the processor with a single address latch if a standard, nonmulti- plexed bus is desired for the system. Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4. (See Figure 5). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a “Not Ready” indication is given by the addressed device, “wait” states (TW) are inserted between T3 and T4. Each inserted “wait” state is of the same duration as a CLK cycle. Periods can occur between 80C88 driven bus cycles. These are referred to as “idle” states (TI), or inactive CLK cycles. The processor uses these cycles for internal housekeeping. During T1 of any bus cycle, the ALE (Address latch enable) signal is emitted (by either the processor or the 82C88 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status infor- mation for the cycle may be latched. Status bits S0, S1, and S2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to Table 2. Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 through T4. S3 and S4 indicate which segment register was used to this bus cycle in forming the address according to Table 3. S5 is a reflection of the PSW interrupt enable bit. S6 is always equal to 0. FIGURE 18. BASIC SYSTEM TIMING (4 + NWAIT) = TCY T1 T2 T3 T4 TWAIT T1 T2 T3 T4 TWAIT (4 + NWAIT) = TCY GOES INACTIVE IN THE STATE JUST PRIOR TO T4 A19-A16 S6-S3 A7-A0 D15-D0 VALID A7-A0 DATA OUT (D7-D0) READY READY WAIT WAIT MEMORY ACCESS TIME ADDR STATUS CLK ALE S2-S0 ADDR DATA RD, INTA READY DT/R DEN WP S6-S3 A19-A16 A15-A8 ADDR A15-A8 BUS RESERVED FOR DATA IN 80C88 |
Codice articolo simile - CS80C88-2 |
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Descrizione simile - CS80C88-2 |
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