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AD5310 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD5310 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 16 page Data Sheet AD5310 Rev. B | Page 11 of 16 THEORY OF OPERATION D/A SECTION The AD5310 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Because there is no reference input pin, the power supply (VDD) acts as the reference. Figure 23 shows a block diagram of the DAC architecture. Figure 23. DAC Architecture Because the input coding to the DAC is straight binary, the ideal output voltage is given by × = 1024 D V V DD OUT where D is the decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 1023. Figure 24. Resistor String RESISTOR STRING The resistor string section is shown in Figure 24. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which results in an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 11 and Figure 12. The slew rate is 1 V/µs with a half-scale settling time of 6 µs with the output loaded. SERIAL INTERFACE The AD5310 has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5310 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 2.4 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part. As previously mentioned, however, it must be brought high again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 16 bits wide (see Figure 25). The first two bits are don’t cares. The next two bits are control bits that control which mode of operation the part is in (normal mode or one of the three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next 10 bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. Finally, the last two bits are don’t cares. Figure 25. Input Register Contents |
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