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AD5255 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD5255 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 20 page AD5255 Rev. A | Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 NC = NO CONNECT A1_RDAC A0_RDAC RS SDA SCL WP A0_EE TEST0 (NC) TEST1 (NC) TEST2 (NC) A0 VDD TEST3 (NC) DGND VSS B2 W2 A2 W0 B0 A1 W1 B1 A1_EE AD5255 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 A0_EE I2C Device Address 0 for EEMEM. 2 A1_RDAC I2C Device Address 1 for RDAC. 3 A0_RDAC I2C Device Address 0 for RDAC. 4 RS Resets the scratchpad register with current contents of the EEMEM register. Factory defaults to midscale before any programming. 5 WP Write Protect. When active low, WP prevents any changes to the present register contents, except that RESET and Command 1 and Command 8 still refresh the RDAC register from EEMEM. 6 SCL Serial Input Register Clock. Shifts in one bit at a time on the positive clock edges. 7 SDA Serial Data Input. Shifts in one bit at a time on the positive clock edges. The MSB is loaded first. 8 DGND Ground. Logic ground reference. 9 VSS Negative Supply. Connect to 0 V for single-supply applications. 10 A2 A terminal of RDAC2. 11 W2 Wiper terminal of RDAC2. 12 B2 B terminal of RDAC2. 13 A1 A terminal of RDAC1. 14 W1 Wiper terminal of RDAC1. 15 B1 B terminal of RDAC1. 16 B0 B terminal of RDAC0. 17 W0 Wiper terminal of RDAC0. 18 A0 A terminal of RDAC0. 19 VDD Positive Power Supply. 20 TEST3 (NC) Test Pin 3. Do not connect. 21 TEST2 (NC) Test Pin 2. Do not connect. 22 TEST1 (NC) Test Pin 1. Do not connect. 23 TEST0 (NC) Test Pin 0. Do not connect. 24 A1_EE I2C Device Address 1 for EEMEM. |
Codice articolo simile - AD5255_15 |
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Descrizione simile - AD5255_15 |
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