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74LVC1G14GM Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74LVC1G14GM Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 20 page 74LVC1G14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 12 — 6 August 2012 7 of 20 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 13. Waveforms Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The data input (A) to output (Y) propagation delays mna640 tPHL tPLH VM VM A input Y output GND VI VOH VOL Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 V CC 0.5 V CC 2.3 V to 2.7 V 0.5 V CC 0.5 V CC 2.7V 1.5V 1.5V 3.0V to 3.6V 1.5V 1.5V 4.5 V to 5.5 V 0.5 V CC 0.5 V CC Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Test circuit for measuring switching times VEXT VCC VI VO mna616 DUT CL RT RL RL G |
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