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74VHC74MTC Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74VHC74MTC Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 10 page ©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC74 Rev. 1.3.1 2 Connection Diagram Pin Description Logic Symbol IEEE/IEC Truth Table Note: 1. This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state. Pin Names Description D1, D2 Data Inputs CK1, CK2 Clock Pulse Inputs CLR1, CLR2 Direct Clear Inputs PR1, PR2 Direct Preset Inputs Q1, Q1, Q2, Q2 Output Inputs Outputs Function CLR PR DCK Q Q LH XX LH Clear HL XX HL Preset LL X X H(1) H(1) HH L L H HH H H L HH X Qn Qn No Change |
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