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SL28EB742 Scheda tecnica(PDF) 6 Page - Silicon Laboratories |
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SL28EB742 Scheda tecnica(HTML) 6 Page - Silicon Laboratories |
6 / 43 page SL28EB742 6 Rev. 1.0 166 MHz CPU Period TPERIOD Measured at 0 V differential at 0.1s 5.99940 6.00060 ns 166 MHz CPU Period, SSC TPERIODSS Measured at 0 V differential at 0.1s 6.01444 6.01564 ns 166 MHz CPU Absolute period TPERIODAbs Measured at 0 V differential at 1 clock 5.91440 6.08560 ns 166 MHz CPU Absolute period, SSC TPERIODSSAbs Measured at 0 V differential at 1 clock 5.91444 6.11572 ns CPU Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 85 ps CPU Cycle to Cycle Jitter for CPU 2 TCCJ (CPU2) Measured at 0 V differential — 125 ps CPU0 to CPU1 skew Skew Measured at 0 V differential — 100 ps Long-term Accuracy LACC Measured at 0 V differential — 100 ppm CPU Rising/Falling Slew rate TR / TF Measured differentially from ±150 mV 2.5 8 V/ns Rise/Fall Matching TRFM Measured single-endedly from ±75 mV —20 % Voltage High VHIGH 1.15 V Voltage Low VLOW –0.3 — V Crossing Point Voltage at 0.7 V Swing VOX 300 550 mV SRC at 0.7 V SRC Duty Cycle TDC Measured at 0 V differential 45 55 % 100 MHz SRC Period TPERIOD Measured at 0 V differential at 0.1s 9.99900 10.0010 ns 100 MHz SRC Period, SSC TPERIODSS Measured at 0 V differential at 0.1s 10.02406 10.02607 ns 100 MHz SRC Absolute Period TPERIODAbs Measured at 0 V differential at 1 clock 9.87400 10.1260 ns 100 MHz SRC Absolute Period, SSC TPERIODSSAbs Measured at 0 V differential at 1 clock 9.87406 10.1762 ns Any SRC Clock Skew from the earliest bank to the latest bank TSKEW(win- dow) Measured at 0 V differential — 3.0 ns SRC Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 85 ps SRC Long Term Accuracy LACC Measured at 0 V differential — 100 ppm SRC Rising/Falling Slew Rate TR / TF Measured differentially from ±150 mV 2.5 8 V/ns Table 3. AC Electrical Specifications (Continued) Parameter Symbol Test Condition Min Max Unit |
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