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SL28EB742 Scheda tecnica(PDF) 5 Page - Silicon Laboratories |
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SL28EB742 Scheda tecnica(HTML) 5 Page - Silicon Laboratories |
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5 / 43 page  SL28EB742 Rev. 1.0 5 Table 3. AC Electrical Specifications Parameter Symbol Test Condition Min Max Unit Long-term Accuracy LACC Measured at VDD/2 differential — 250 ppm Clock Input CLKIN Duty Cycle TDC Measured at VDD/2 47 53 % CLKIN Rise and Fall Times TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 350 ps Input High Voltage VIH XIN / CLKIN pin 2 VDD+0.3 V Input Low Voltage VIL XIN / CLKIN pin — 0.8 V Input High Current IIH XIN / CLKIN pin, VIN = VDD 35 µA Input Low Current IIL XIN / CLKIN pin, 0 < VIN <0.8 –35 — µA CPU at 0.7 V CPU Duty Cycle TDC Measured at 0 V differential 45 55 % 83.33 MHz CPU Period TPERIOD Measured at 0 V differential at 0.1s 11.99880 12.00120 ns 83.33 MHz CPU Period, SSC TPERIODSS Measured at 0 V differential at 0.1s 12.02887 2 12.03128 ns 83.33 MHz CPU Absolute Period TPERIODAbs Measured at 0 V differential at 1clock 11.18969 12.16344 ns 83.33 MHz CPU Absolute Period, SSC TPERIODSSAbs Measured at 0 V differential at 1 clock 11.89687 12.16344 ns 100 MHz CPU Period TPERIOD Measured at 0 V differential at 0.1s 9.99900 10.0010 ns 100 MHz CPU Period, SSC TPERIODSS Measured at 0 V differential at 0.1s 10.02406 10.02607 ns 100 MHz CPU Absolute Period TPERIODAbs Measured at 0 V differential at 1clock 9.87400 10.1260 ns 100 MHz CPU Absolute Period, SSC TPERIODSSAbs Measured at 0 V differential at 1 clock 9.87406 10.1762 ns 133 MHz CPU Period TPERIOD Measured at 0 V differential at 0.1s 7.49925 7.50075 ns 133 MHz CPU Period, SSC TPERIODSS Measured at 0 V differential at 0.1s 7.51804 7.51955 ns 133 MHz CPU Absolute Period TPERIODAbs Measured at 0 V differential at 1 clock 7.41425 7.58575 ns 133 MHz CPU Absolute period, SSC TPERIODSSAbs Measured at 0 V differential at 1 clock 7.41430 7.62340 ns |
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