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TSB81BA3IPFPEP Scheda tecnica(PDF) 4 Page - Texas Instruments |
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TSB81BA3IPFPEP Scheda tecnica(HTML) 4 Page - Texas Instruments |
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4 / 58 page  TSB81BA3EP IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER SGLS194A − SEPTEMBER 2003 − REVISED JULY 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts LKON/DS2 for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1. |
Codice articolo simile - TSB81BA3IPFPEP |
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