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ADF7021BCPZ-RL7 Scheda tecnica(PDF) 10 Page - Analog Devices |
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ADF7021BCPZ-RL7 Scheda tecnica(HTML) 10 Page - Analog Devices |
10 / 64 page ADF7021 Data Sheet Rev. B | Page 10 of 64 Parameter Min Typ Max Unit Test Conditions/Comments LNA INPUT IMPEDANCE RFIN to RFGND fRF = 915 MHz 24 − j60 Ω fRF = 868 MHz 26 − j63 Ω fRF = 450 MHz 63 − j129 Ω fRF = 426 MHz 68 − j134 Ω fRF = 315 MHz 96 − j160 Ω fRF = 175 MHz 178 − j190 Ω 1 Calibration of the image rejection used an external RF source. 2 For received signal levels < −100 dBm, it is recommended to average the RSSI readback value over a number of samples to improve the RSSI accuracy at low input powers. 3 Filtered conductive receive spurious emissions measured on the EVAL-ADF7021DBx, which includes a T-stage harmonic filter (two inductors and one capacitor). DIGITAL SPECIFICATIONS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments TIMING INFORMATION Chip Enabled to Regulator Ready 10 µs CREG = 100 nF Chip Enabled to Tx Mode 32-bit register write time = 50 µs TCXO Reference 1 ms XTAL 2 ms Chip Enabled to Rx Mode 32-bit register write time = 50 µs, IF filter coarse calibration only TCXO Reference 1.2 ms XTAL 2.2 ms Tx to Rx Turnaround Time 300 µs + (5 × tBIT) Time to synchronized data out, includes AGC settling and CDR synchronization; see AGC Information and Timing section for more details; tBIT = data bit period LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 µA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH DVDD − 0.4 V IOH = 500 µA Output Low Voltage, VOL 0.4 V IOL = 500 µA CLKOUT Rise/Fall 5 ns CLKOUT Load 10 pF |
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