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CDB5351 Scheda tecnica(PDF) 7 Page - Cirrus Logic |
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CDB5351 Scheda tecnica(HTML) 7 Page - Cirrus Logic |
7 / 24 page CS5351 DS565PP2 7 3.2.1 Master Mode In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 2. Refer to Table 2 for common master clock frequencies ÷ 128 ÷ 256 ÷ 64 M0 M1 LRCK Output (Equal to Fs) Single Speed Quad Speed Double Speed 00 01 10 ÷ 2 ÷ 4 ÷ 1 SCLK Output Single Speed Quad Speed Double Speed 00 01 10 ÷ 2 ÷ 1 0 1 MCLK MDIV Figure 2. CS5351 Master Mode Clocking SAMPLE RATE (kHz) MDIV = 0 MCLK (MHz) MDIV = 1 MCLK (MHz) 32 8.192 16.384 44.1 11.2896 22.5792 48 12.288 24.576 64 8.192 16.384 88.2 11.2896 22.5792 96 12.288 24.576 176.4 11.2896 22.5792 192 12.288 24.576 Table 2. CS5351 Common Master Clock Frequencies |
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