Motore di ricerca datesheet componenti elettronici |
|
CS5351-BS Scheda tecnica(PDF) 8 Page - Cirrus Logic |
|
CS5351-BS Scheda tecnica(HTML) 8 Page - Cirrus Logic |
8 / 24 page CS5351 8 DS565PP2 3.2.2 Slave Mode LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3 for required clock ratios. *Available when MDIV = 1 (for Master Mode) Table 3. CS5351 Slave Mode Clock Ratios 3.3 Power-up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de- lay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance. 3.4 Analog Connections The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3 which shows the sug- gested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Please see the Addendum at the end of the datasheet for an analog input buffer that can be used with both the CS5351 as well as the CS5361 with a simple change in the bill of materials. Single Speed Mode Fs = 2kHz to 50kHz Double Speed Mode Fs = 50kHz to 100kHz Quad Speed Mode Fs = 100kHz to 192kHz MCLK/LRCK Ratio 256x (512x)* 128x (256x)* 128x (256x)* SCLK/LRCK Ratio 32x, 64x, 128x 32x, 64x 64x |
Codice articolo simile - CS5351-BS |
|
Descrizione simile - CS5351-BS |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |