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CDB4362 Scheda tecnica(PDF) 10 Page - Cirrus Logic |
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CDB4362 Scheda tecnica(HTML) 10 Page - Cirrus Logic |
10 / 40 page CS4362 10 SWITCHING CHARACTERISTICS - CONTROL PORT - I2CFORMAT (For KQ TA =-10 to +70 °C; For BQ TA =-40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1= VLC, CL =30pF) Notes: 20. Data must be held for sufficient time to bridge the transition time, tfc,of SCL. 21. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 22. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 20) thdd 0- µs SDA Setup time to SCL Rising tsud 250 - ns Rise Time of SCL and SDA trc,trc -1 µs Fall Time SCL and SDA tfc,tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling (Note 21) tack -(Note 22) ns 15 256 Fs × --------------------- 15 128 Fs × --------------------- 15 64 Fs × ------------------ t buf t hd st t lo w t hdd t high t sud Stop S t a rt SD A SC L t irs RS T t hd st t rc t fc t sust t su sp St a r t Sto p R epe at e d t rd t fd t ack Figure 3. Control Port Timing - I 2CFormat |
Codice articolo simile - CDB4362 |
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Descrizione simile - CDB4362 |
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