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CS22220 Scheda tecnica(PDF) 9 Page - Cirrus Logic |
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CS22220 Scheda tecnica(HTML) 9 Page - Cirrus Logic |
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9 / 34 page  CS22220 Wireless PCMCIA Controller 9 of 34 DS557PP2 Rev. 3.0 www.cirrus.com This section provides detailed information on the CS22220 signals. The signal descriptions are useful for hardware designers who are interfacing the CS22220 with other devices. System Memory Interface The system memory interface supports standard SDRAM interface, async SRAM and FLASH. There are a total of 38 signals in this interface. SMCLK Output System mem clock for SDRAM. Currently the interface supports 100 MHz for a maximum bandwidth of 200Mbytes/sec. nSMCS0 Output Chip select bit 0. This signal is used to select or deselect the SDRAM for command entry. When SMNCS is low it qualifies the sampling of nSMRAS, nSMCAS and nSMWE. Also, used as testmode(2) when NTEST pin is '0'. nSMCS1 Output Chip select bit 1. nBRCE Output Chip select for ROM access. This signal is used to select or deselect the boot ROM memory. nSMRAS Output Row address select. Used in combination with nSMCAS, nSMWE and nSMCS to specify which SDRAM page to open for access. Also used during reset to latch in the strap value for clk_bypass; if set to a '1' implies bypassing clock module; whatever clk is applied on the input clock is used for memclk and ctlclk. Also shared as the ROMOE signal. nSMCAS Output Column address select. Used in combination with nSMRAS, nSMWE and nSMCS to specify which piece of data to access in selected page. Also used during reset to latch in the strap value for same_freq; if set to a '1' implies internal mem_clk and arm_clk are running at the same frequency and 180 degrees out of phase. nSMWE Output Write enable. Used in combination with nSMRAS, nSMCAS, and nSMWE to specify whether the current cycle is a read or a write cycle. Also used during reset to latch in the strap value for tst_bypass; if set to a '1' implies PLL bypass. Also shared as the ROMWE to do flash programming. |
Codice articolo simile - CS22220 |
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