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CS22210 Scheda tecnica(PDF) 5 Page - Cirrus Logic |
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CS22210 Scheda tecnica(HTML) 5 Page - Cirrus Logic |
5 / 31 page CS22210 PCI/USB Wireless Controller 5 of 31 D556PP2 Rev. 3.0 www.cirrus.com 3.1 Embedded ARM Core and System Support Logic The processing elements of the CS22210 include the ARM7TDMI core and its associated system control logic. The ARM processor and system controller consist of a memory management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt controller, and 2 general purpose timers. The ARM processor and integrated system support logic provide the necessary execution engine to support a real time multi-tasking operating system, the network protocol stack, and firmware services. In addition, system performance monitor logic is included to aid in system performance fine-tuning (e.g. cache hit, CPI numbers). Memory Management Unit ARM instructions and data are fetched from system memory a cache-line (4/8 – Dwords /Programmable) at a time when caching is turned on. During a cache line fill, critical word data, i.e., the access that caused the miss, is forwarded to the ARM and also written into the data RAM cache. The non-critical words in the line fetched following the critical word are then written to the cache on a Dword basis, as they become available. Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write posts use the sequential addressing feature on the memory bus. With dual buffering an out of sequence write will post to one write buffer while the other buffer is flushed to memory. There is one 8Dword Read Buffer in the MEM block. The buffer is used for both cacheable and non-cacheable memory space. Interrupt Controller The interrupt controller provides two interrupt channels to the ARM processor. One interrupt channel is presented to the ARM on its nFIQ, and the other channel is presented on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both channels operate in identical but independent fashion. The FIQ channel has a higher priority on the ARM processor than the IRQ channel. The interrupt controller includes a CONTROL register for each logical interrupt in the ARM complex. The CONTROL register serves the following main purposes: • Provides the mapping between the EXT_INT inputs (physical interrupts) and the logical interrupt • Selects the particular type of signaling expected on the EXT_INT inputs: level, edge, active level high/low etc. • Enables or disable a logical interrupt |
Codice articolo simile - CS22210 |
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Descrizione simile - CS22210 |
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