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CS5111YDWF24 Scheda tecnica(PDF) 4 Page - Cherry Semiconductor Corporation |
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CS5111YDWF24 Scheda tecnica(HTML) 4 Page - Cherry Semiconductor Corporation |
4 / 10 page 4 Typical Performance Characteristics 0A 20mA 40mA 60mA 80mA 100mA 3.5mA 4.0mA 4.5mA ILIN -30mA -40mA 0A 0.5A ISW -20mA -10mA 0A 1.0A 1.5A 2.0A ISW 0A 0.5A 1.0A 1.5A 2.0A 0.4V 0.0V 0.6V 0.8V 1.2V 1.0V 0.2V 1.4V Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION 40 0 0 COSC (pF) 80 120 160 1000 20 60 100 140 2000 3000 500 1500 2500 180 Figure 1a. 5V Regulator Bias Current vs. Load Current. Figure 1b. Supply Current vs. Switch Current. Figure 1c. Switch Saturation Voltage. Figure 1d. Oscillator Frequency (kHz) vs. COSC (pF), assuming RBIAS = 64.9kΩ. 24 Lead SO Wide 1VIN Supply Voltage. 2, 3 NC No connection. 4VSW Collector of NPN power switch for switching regulator section. 5,6,7,8,17,18,19,20 Gnd Connected to the heat removing leads. 9VFB1 Feedback input voltage 1 (referenced to 1.25V) 10 VFB2 Feedback input voltage 2 (referenced to 1.25V) 11 SELECT Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to Gnd to select VFB1. 12 COMP Output of the transconductance error amplifier. 13 COSC A capacitor connected to Gnd sets the switching frequency. Refer to Figure 1d. 14 WDI Watchdog input. Active on falling edge. 15 CDelay A capacitor connected to Gnd sets the Power On Reset and Watchdog time. 16 output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued. 21 IBIAS A resistor connected to Gnd sets internal bias currents as well as the COSC and CDelay charge currents. 22 VLIN Regulated 5V output from the linear regulator section. 23 VREG Input voltage to the linear regulator and the internal supply cir- cuitry. 24 Logic level input to shut down the switching regulator. ENABLE RESET RESET |
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