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HCPL0637 Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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HCPL0637 Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 18 page ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com HCPL06XX Rev. 1.0.9 2 Truth Table (Positive Logic) *Dual channel devices or single channel devices with pin 7 not connected. A 0.1µF bypass capacitor must be connected between pins 8 and 5. (See note 1) Input Enable Output HH L LH H HLH LL H H* NC* L* L* NC* H* Single-channel circuit drawing (HCPL0600, HCPL0601 and HCPL0611) Dual-channel circuit drawing (HCPL0637, HCPL0638 and HCPL0639) 1 2 3 4 5 6 7 8 N/C _ V CC V E V O GND + N/C V F 1 2 3 4 5 6 7 8 + _ V F1 V CC V 01 V 02 GND V F2 _ + |
Codice articolo simile - HCPL0637 |
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