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ADV7123SCP170EP-RL Scheda tecnica(PDF) 8 Page - Analog Devices |
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ADV7123SCP170EP-RL Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 12 page ADV7123-EP Rev. 0 | Page 8 of 12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 COMP VAA VAA IOB GND GND VREF IOB IOG IOG IOR IOR BLANK NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE PACKAGE MUST BE SOLDERED TO THE GROUND PLANE TO INCREASE THE RELIABILITY OF THE SOLDER JOINTS AND TO MAXIMIZE THE THERMAL CAPABILITY OF THE PACKAGE. SYNC ADV7123-EP TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 11 12 35 36 34 33 32 31 30 29 28 27 26 25 PIN 1 INDICATOR Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 to 10, 14 to 23, 39 to 48 G0 to G9, B0 to B9, R0 to R9 Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular printed circuit board (PCB) power or ground plane. 11 BLANK Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs— IOR, IOB, and IOG—to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. When BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored. 12 SYNC Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current source. The sync current is internally connected to the IOG analog output. SYNC does not override any other control or data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0. 13, 29, 30 VAA Analog Power Supply (3.3 V ± 10%). All VAA pins on the ADV7123-EP must be connected. 24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and BLANK pixel and control inputs. Typically, the CLOCK input is the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. 25, 26 GND Ground. The GND pins must be connected. 27, 31, 33 IOB, IOG, IOR Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω coaxial cable. If the complementary outputs are not required, these outputs should be tied to ground. 28, 32, 34 IOB, IOG, IOR Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. 35 COMP Compensation Pin for the Internal Reference Amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and VAA. 36 VREF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). The VREF pin is normally terminated to VAA through a 0.1 μF capacitor. However, the ADV7123-EP can be overdriven by an external 1.23 V reference (AD1580), if required. |
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