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AD5228BUJZ50-RL7 Scheda tecnica(PDF) 4 Page - Analog Devices

Il numero della parte AD5228BUJZ50-RL7
Spiegazioni elettronici  32-Position Manual Up/Down Control Potentiometer
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5228BUJZ50-RL7 Scheda tecnica(HTML) 4 Page - Analog Devices

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AD5228
Rev. A | Page 4 of 20
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS 4, 9, 10, 11
Built-in Debounce and Settling Time 12
tDB
6
ms
PU Low Pulse Width
tPU
12
ms
PD Low Pulse Width
tPD
12
ms
PU High Repetitive Pulse Width
tPU_REP
1
μs
PD High Repetitive Pulse Width
tPD_REP
1
μs
Autoscan Start Time
tAS_START
PU or PD = 0 V
0.6
0.8
1.2
s
Autoscan Time
tAS
PU or PD = 0 V
0.16
0.25
0.38
s
Bandwidth –3 dB
BW_10
RAB = 10 kΩ, midscale
460
kHz
BW_50
RAB = 50 kΩ, midscale
100
kHz
BW_100
RAB = 100 kΩ, midscale
50
kHz
Total Harmonic Distortion
THD
VA = 1 V rms, RAB = 10 kΩ,
VB = 0 V dc, f = 1 kHz
0.05
%
Resistor Noise Voltage
eN_WB
RWB = 5 kΩ, f = 1 kHz
14
nV/
√Hz
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 Guaranteed by design and not subject to production test.
5 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
7
PU and PD have 100 kΩ internal pull-up resistors, IDD_ACT = VDD/100 kΩ + IOSC (internal oscillator operating current) when PU or PD is connected to ground.
8 PDISS is calculated based on IDD_STBY × VDD only. IDD_ACT duration should be short. Users should not hold PU or PD pin to ground longer than necessary to elevate power
dissipation.
9 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
10 All dynamic characteristics use VDD = 5 V.
11 Note that all input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured
using VDD = 5 V.
12 The debouncer keeps monitoring the logic-low level once PU is connected to ground. Once the signal lasts longer than 11 ms, the debouncer assumes the last
bounce is met and allows the AD5228 to increment by one step. If the PU signal remains at low and reaches tAS_START, the AD5528 increments again, see Figure 7. Similar
characteristics apply to PD operation.
INTERFACE TIMING DIAGRAMS
RWB
PU
tDB
tPD
tPD_REP
RWB
PU
tPU
tPU_REP
tDB
Figure 2. Increment RWB in Discrete Steps
Figure 4. Decrement RWB in Discrete Steps
RWB
PD
tDB
tAS
tAS_START
RWB
PU
tDB
tAS
tAS_START
Figure 5. Decrement RWB in Autoscan Mode
Figure 3. Increment RWB in Autoscan Mode


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