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CAT24C023PI-30TE13 Scheda tecnica(PDF) 6 Page - Catalyst Semiconductor

Il numero della parte CAT24C023PI-30TE13
Spiegazioni elettronici  Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
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Produttore elettronici  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT24C023PI-30TE13 Scheda tecnica(HTML) 6 Page - Catalyst Semiconductor

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CAT24C163/083/043/023
6
Advanced
Doc. No. 25080-00 3/98 M-1
Hardware Data Protection
The 24CXXX is designed with the following hardware
data protection features to provide a high degree of data
integrity.
(1) The 24CXXX features a WP pin. When WP pin is tied
high the entire memory array becomes write protected
(read only).
(2) The VCC sense provides write protection when VCC
falls below the reset threshold value (VTH). The VCC lock
out inhibits writes to the serial EEPROM whenever VCC
falls below (power down) VTH or until VCC reaches the
reset threshold (power up) VTH.
Reset Threshold Voltage
From the factory the 24CXXX is offered in five different
variations of reset threshold voltages. They are 4.50-
4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-
2.70V. To provide added flexibility to design engineers
using this product, the 24CXXX is designed with an
additional feature of programming the reset threshold
voltage. This allows the user to change the existing
reset threshold voltage to one of the other four reset
threshold voltages. Once the reset threshold voltage is
selected it will not change even after cycling the power,
unless the user uses the programmer to change the
reset threshold voltage. However, the programming
function is available only through third party programmer
manufacturers. Please call Catalyst for a list of program-
mer manufacturers who support this function.
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
Figure 3. Write Cycle Timing
START BIT
SDA
STOP BIT
SCL
Figure 4. Start/Stop Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 2. Bus Timing


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