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IRF7769L2TR1PBF Scheda tecnica(PDF) 6 Page - International Rectifier |
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IRF7769L2TR1PBF Scheda tecnica(HTML) 6 Page - International Rectifier |
6 / 11 page IRF7769L2TR/TR1PbF 6 www.irf.com Fig 17. Diode Reverse Recovery Test Circuit for N-Channel HEXFET® Power MOSFETs Fig 15. Typical Avalanche Current Vs.Pulsewidth Fig 16. Maximum Avalanche Energy Vs. Temperature Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 19a, 19b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·ta 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) 0.1 1 10 100 1000 0.05 Duty Cycle = Single Pulse 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤ j = 25°C and Tstart = 150°C. 0.01 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150°C and Tstart =25°C (Single Pulse) 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (°C) 0 40 80 120 160 200 240 280 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 74A P.W. Period di/dt Diode Recovery dv/dt Ripple ≤ 5% Body Diode Forward Drop Re-Applied Voltage Reverse Recovery Current Body Diode Forward Current VGS=10V VDD ISD Driver Gate Drive D.U.T. ISD Waveform D.U.T. VDS Waveform Inductor Curent D = P.W. Period * VGS = 5V for Logic Level Devices * Inductor Current Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer • di/dt controlled by RG • Driver same type as D.U.T. • ISD controlled by Duty Factor "D" • D.U.T. - Device Under Test + - + + + - - - RG VDD D.U.T |
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