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L6717TR Scheda tecnica(PDF) 9 Page - STMicroelectronics

Il numero della parte L6717TR
Spiegazioni elettronici  High-efficiency hybrid AM2r2 controller with I2C interface and embedded drivers
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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L6717
Pins description and connection diagrams
Doc ID 17326 Rev 1
9/56
5
FB
CORE error amplifier inverting input.
Connect with a resistor RFB to VSEN and with an RF - CF to COMP. Droop current for
voltage positioning is sourced from this pin.
6VSEN
CORE output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the load for remote sensing. See Section 8 for details.
7FBG
CORE remote ground sense.
Connect to the negative side of the load for remote sensing. See Section 11 for proper
layout of this connection.
8LTB
LTB Technology® input pin.
Connect through an RLTB - CLTB network to the regulated voltage (CORE section) to
detect load transient. See Section 12 for details.
9
NB_COMP
NB error amplifier output.
Connect with an RF_NB - CF_NB to NB_FB.
The NB section and/or the device cannot be disabled by grounding this pin.
10
NB_FB
NB error amplifier inverting input.
Connect with a resistor RFB_NB to NB_VSEN and with an RF_NB - CF_NB to NB_COMP.
Droop current for voltage positioning is sourced from this pin.
11
NB_VSEN
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the NB load to perform remote sensing. See Section 11 for proper layout of this
connection.
12
NB_FBG
NB remote ground sense.
Connect to the negative side of the load to perform remote sense. See Section 11 for
proper layout of this connection.
13
ILIM
CORE over current pin.
A current ILIM=DCR/RG*IOUT proportional to the current delivered by the CORE
Section is sourced from this pin. The OC threshold is programmed by connecting a
resistor RILIM to SGND. When the generated voltage crosses the OC_TOT threshold
(VOC_TOT = 2.5V Typ) the device latches with all MOSFETs OFF (to recover, cycle
VCC or the EN pin).
This pin is monitored for dynamic phase management.
Filter with proper capacitor to provide OC masking time; do not exceed 30
μsec. See
Section 8.4.1 for details.
14
OSC / EN /
FLT
OSC: It allows programming the switching frequency FSW of both sections. Switching
frequency can be increased according to the resistor ROSC connected to SGND with a
gain of 9.1kHz/µA (see Section 9 for details). If floating, the switching frequency is
200kHz per phase.
EN: Pull-low (tie to GND) to disable the device. When set free, the device immediately
checks for the VID1 status to determine the SVI / PVI protocol to be adopted and
configures itself accordingly.
FLT: The pin is internally forced high (3.3V) in case of an OV / UV fault. To recover
from this condition, cycle VCC or the EN pin.
To enable/disable the IC drive OSC/EN/FAUT pin by an open drain circuit.
Table 2.
Pin description (continued)
Pin#
Name
Function


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