8

®

DAC2814

DISCUSSION OF

SPECIFICATIONS

INPUT CODES

All digital inputs of the DAC2814 are TTL and 5V CMOS

compatible. Input codes for the DAC2814 are either USB

(Unipolar Straight Binary) or BOB (Bipolar Offset Binary)

depending on the mode of operation. See Figure 3 for

±10V

bipolar connection. See Figures 4 and 5 for 0 to 10V and 0

to –10V unipolar connections.

UNIPOLAR AND BIPOLAR

OUTPUTS FOR SELECTED INPUT

DIGITAL INPUT

UNIPOLAR (USB)

BIPOLAR (BOB)

+Full scale

+Full scale

+1/2 Full scale

Zero

+1/2 Full scale – 1 LSB

Zero – 1 LSB

Zero

–Full scale

DIGITAL CROSSTALK

Digital crosstalk is the glitch impulse measured at the output

of one DAC due to a full scale transition on the other

DAC—see Typical Performance Curves. It is dominated by

digital coupling. Also, the integrated area of the glitch pulse

is specified in nV–s. See table of electrical specifications.

DIGITAL FEEDTHROUGH

Digital feedthrough is the noise at a DAC output due to

activity on the digital inputs—see Typical Performance

Curves.

OPERATION

DACs can be updated simultaneously or independently as

required. Data are transferred on falling clock edges into a

24-bit shift register. DAC B MSB is loaded first. Data are

transferred to the DAC registers when the LATCH signals

are brought low. The data are latched when the LATCH

signals are brought high. Both LATCH signals may be tied

together to allow simultaneous update of the DACs if re-

quired. The output of the DAC shift register is provided to

allow cascading of several DACS on the same bit stream.

By using separate signals for LATCH A and LATCH B, it

is possible to update either one of the two DACs every 12

clock cycles.

When CLR is brought low, the input shift registers are

LATCH is brought low after CLR, the DACs are updated

the output.

CIRCUIT DESCRIPTION

Each of the two DACs in the DAC2814 consists of a CMOS

logic section, a CMOS DAC cell, and an output amplifier.

One buried-zener +10.0V reference and a reference inverter

(for a –10.0V reference) are shared by both DACs.

Figure 1 is a simplified circuit for a DAC cell. An R, 2R

Current from the ladder is switched either to I

by 12 single-pole double-throw CMOS switches. This main-

tains constant current in each leg of the ladder regardless of

stant (it can be driven by either a voltage or current refer-

ence). The reference can be either positive or negative

polarity with a range of up to

±10V.

INTEGRAL OR RELATIVE LINEARITY

This term, also know as end point linearity, describes the

transfer function of analog output to digital input code.

Integral linearity error is the deviation of the analog output

versus code transfer function from a straight line drawn

through the end points.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1

LSB change in the output voltage when the input code

changes by 1 LSB. A differential nonlinearity specification

of

±1 LSB maximum guarantees monotonicity.

UNIPOLAR OFFSET ERROR

The output voltage for code 000

unipolar mode of operation.

BIPOLAR ZERO ERROR

bipolar mode of operation.

GAIN ERROR

from the ideal span of 10V – 1 LSB (unipolar mode) or 20V

– 1 LSB (bipolar mode). The gain error is specified with and

without the internal +10V reference error included.

OUTPUT SETTLING TIME

The time required for the output voltage to settle within a

percentage-of-full-scale error band for a full scale transition.

Settling to

±0.012% (1/2 LSB) is specified for the DAC2814.

DIGITAL-TO-ANALOG GLITCH

Ideally, the DAC output would make a clean step change in

response to an input code change. In reality glitches occur

during the transition. See Typical Performance Curves.

D11

(MSB)

D10

D9

D0

(LSB)

AGND

I

RR

R

2R

2R

2R

2R

2R

R

OUT

V

REF

R

FB

FIGURE 1. Simplified Circuit Diagram of DAC Cell.