PD104SLG

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Page:8

Recommended Transmitter (THC63LVDM63A Thine) to PD104SLG interface Assignment :

Input terminal of

THC63LVDM63A

Graphic controller output signal

To PD104SLG

interface

terminal(Symbol)

Symbol

No.

Symbol

Function

Output signal

symbol

TIN0

44

R0

Red pixel data (LSB)

TIN1

45

R1

Red pixel data

TIN2

47

R2

Red pixel data

Tout0-

No.5 : IN0-

TIN3

48

R3

Red pixel data

TIN4

1

R4

Red pixel data

Tout0+

No.6 : IN0+

TIN5

3

R5

Red pixel data(MSB)

TIN6

4

G0

Green pixel data (LSB)

TIN7

6

G1

Green pixel data

TIN8

7

G2

Green pixel data

TIN9

9

G3

Green pixel data

Tout1-

No.7 : IN1-

TIN10

10

G4

Green pixel data

TIN11

12

G5

Green pixel data(MSB)

Tout1+

No.8 : IN1+

TIN12

13

B0

Blue pixel data(LSB)

TIN13

15

B1

Blue pixel data

TIN14

16

B2

Blue pixel data

TIN15

18

B3

Blue pixel data

TIN16

19

B4

Blue pixel data

Tout2-

No.9 : IN2-

TIN17

20

B5

Blue pixel data(MSB)

TIN18

22

HSYNC Horizontal sync signal

Tout2+

N0.10 : IN2+

TIN19

23

VSYNC Vertical sync signal

TIN20

25

DENB Compound Synchronization signal

TCLK in

26

CLK

Data sampling clock

TCLK out-

TCLK out+

No.11 : CLK -

No.12 : CLK +

Data stream of IN0-/+, IN1-/+ and IN2-/+

for PD104SLG

LVDS Interface Block Diagram

N

N

N

N

N

N

L

L

0-

0+

1-

1+

2-

2+

K -

K +

D ata

C ontrol

& data

L C D controller

TIN 0~TIN 5

TIN 6~TIN 11

TIN 12~ TIN 17

TIN 18

TIN 19

TIN 20

T C L K IN

R0 ~ R5

G 0 ~ G 5

B0 ~ B5

H sync

V sync

CL K I N

P L L

I

I

I

I

I

I

C

C

PD 104S LG m odule side

C u stom er system side

D E N B

T H C 63L V D M 63A

P-511-525(V:3)