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AD7713AR Scheda tecnica(PDF) 10 Page - Analog Devices |
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AD7713AR Scheda tecnica(HTML) 10 Page - Analog Devices |
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10 / 28 page  REV. D –10– AD7713 PGA Gain G2 Gl G0 Gain 00 01 (Default Condition after the Internal Power-On Reset) 00 12 01 04 01 18 10 016 10 132 11 064 11 1128 Channel Selection CH1 CH0 Channel 00 AIN1 (Default Condition after the Internal Power-On Reset) 01 AIN2 10 AIN3 Word Length WL Output Word Length 0 16-Bit (Default Condition after the Internal Power-On Reset) 1 24-Bit RTD Excitation Currents RO 0Off (Default Condition after the Internal Power-On Reset) 1On Burn-Out Current BO 0Off (Default Condition after the Internal Power-On Reset) 1On Bipolar/Unipolar Selection (Both Inputs) B/U 0 Bipolar (Default Condition after the Internal Power-On Reset) 1 Unipolar Filter Selection (FS11 to FS0) The on-chip digital filter provides a sinc 3 (or (sinx/x)3) filter response. The 12 bits of data programmed into these bits deter- mine the filter cutoff frequency, the position of the first notch of the filter, and the data rate for the part. In association with the gain selection, it also determines the output noise (and therefore the effective resolution) of the device. The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (fCLK IN/512)/code where code is the decimal equivalent of the code in Bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal fCLK IN of 2 MHz, this results in a first notch frequency range from 1.952 Hz to 205.59 kHz. To ensure correct operation of the AD7713, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figures 2a and 2b show the effect of the filter notch frequency and gain on the effective resolution of the AD7713. The output data rate (or effective conversion time) for the device is equal to the frequency se- lected for the first notch of the filter. For example, if the first notch of the filter is selected at 10 Hz, then a new word is avail- able at a 10 Hz rate or every 100 ms. If the first notch is at 200 Hz, a new word is available every 5 ms. The settling time of the filter to a full-scale step input change is worst case 4 1/(Output Data Rate). This settling time is to 100% of the final value. For example, with the first filter notch at 100 Hz, the settling time of the filter to a full-scale step input change is 400 ms max. If the first notch is at 200 Hz, the settling time of the filter to a full-scale input step is 20 ms max. This settling time can be reduced to 3 l/(Output Data Rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with SYNC low, the settling time will be 3 l/(Output Data Rate). If a change of channels takes place, the settling time is 3 l/(Output Data Rate) regardless of the SYNC input. The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: Filter dB Frequency First Notch Frequency −= × 30 262 . |
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