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DAC707JP Scheda tecnica(PDF) 5 Page - Texas Instruments |
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DAC707JP Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 13 page 5 ® DAC707/708/709 DESCRIPTION OF PIN FUNCTIONS DAC707 Pin DAC708/709 DESIGNATOR DESCRIPTION # DESIGNATOR DESCRIPTION VOUT Voltage output for DAC707 ( ±10V) 1 A2 Latch enable for D/A latch (Active low) VDD Logic supply (+5V) 2 A0 Latch enable for “low byte” input (Active low). When both A0 and A1 are logic “0”, the serial input mode is selected and the serial input is enabled. DCOM Digital common 3 A1 Latch enable for “high byte” input (Active low). When both A0 and A1 are logic “0”, the serial input mode is selected and the serial input is enabled. ACOM Analog common 4 D7 (D15) Input for data bit 7 if enabling low byte (LB) latch or data bit 15 if enabling the high byte (HB) latch. SJ Summing junction of the internal output op amp for the 5 D6 (D14) Input for data bit 6 if enabling LB latch or data bit 14 if DAC707. Offset adjust circuit is connected to the enabling the HB latch. summing junction of the output amplifier. Refer to Block Diagram. GA Gain adjust pin. Refer to Connection Diagram for gain 6 D5 (D13) Data bit 5 (LB) or data bit 13 (HB) adjust circuit. +VCC Positive supply voltage (+15V) 7 D4 (D12) Data bit 4 (LB) or data bit 12 (HB) –VCC Negative supply voltage (–15V) 8 D3 (D11) Data bit 3 (LB) or data bit 11 (HB) CLR Clear line. Sets the input latch to zero and sets the D/A 9 D2 (D10) Data bit 2 (LB) or data bit 10 (HB) latch to the input code that gives bipolar zero on the D/A output (Active low) WR Write control line (Active low) 10 D1 (D9) Data bit 1 (LB) or data bit 9 (HB) A1 Enable for D/A converter latch (Active low) 11 D0 (D8)/SI Data bit 0 (LB) or data bit 8 (HB). Serial input when serial mode is selected. A0 Enable for input latch (Active low) 12 DCOM Digital common D15 (MSB) Data bit 15 (Most Significant Bit) 13 RF2 Feedback resistor for internal or external operational amplifier. Connect to pin 14 when a 10V output range is desired. Leave open for a 20V output range. D14 Data bit 14 14 VOUT Voltage output for DAC709 or feedback resistor for RF1 (DAC708) use with an external output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 ACOM Analog common D12 Data bit 12 16 SJ (DAC709) Summing junction of the internal output op amp for the IOUT (DAC708) DAC709, or the current output for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset. Connect to pin 16 when operating in the bipolar mode. Leave open for unipolar mode. D10 Data bit 10 18 GA Gain adjust pin D9 Data bit 9 19 +VCC Positive supply voltage (+15V) D8 Data bit 8 20 –VCC Negative supply voltage (–15V) D7 Data bit 7 21 CLR Clear line. Sets the high and low byte input registers to zero and, for bipolar operation, sets the D/A register to the input code that gives bipolar zero on the D/A output. (In the unipolar mode, invert the MSB prior to the D/A.) D6 Data bit 6 22 WR Write control line D5 Data bit 5 23 CS Chip select control line D4 Data bit 4 24 VDD Logic supply (+5V) D3 Data bit 3 25 No pin D2 Data bit 2 26 No pin (The DAC708 and DAC709 are in 24-pin packages) D1 Data bit 1 27 No pin D0 (LSB) Data bit 0 (Least Significant Bit) 28 No pin |
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