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SI3445DV-T1-E3 Scheda tecnica(PDF) 2 Page - Vishay Siliconix |
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SI3445DV-T1-E3 Scheda tecnica(HTML) 2 Page - Vishay Siliconix |
2 / 9 page www.vishay.com 2 Document Number: 70820 S09-0766-Rev. C, 04-May-09 Vishay Siliconix Si3445DV Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.45 - 1.0 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 8 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = - 8 V, VGS = 0 V - 1 µA VDS = - 8 V, VGS = 0 V, TJ = 70 °C - 5 On-State Drain Currenta ID(on) VDS ≥ - 5 V, VGS = - 4.5 V - 15 A Drain-Source On-State Resistancea RDS(on) VGS = - 4.5 V, ID = - 5.6 A 0.034 0.042 Ω VGS = - 2.5 V, ID = - 4.7 A 0.048 0.060 VGS = - 1.8 V, ID = - 2.0 A 0.062 0.080 Forward Transconductancea gfs VDS = - 10 V, ID = - 5.6 A 15 S Diode Forward Voltagea VSD IS = - 1.7 A, VGS = 0 V - 0.7 - 1.2 V Dynamicb Total Gate Charge Qg VDS = - 4 V, VGS = - 4.5 V, ID = - 5.6 A 15 25 nC Gate-Source Charge Qgs 3 Gate-Drain Charge Qgd 2 Turn-On Delay Time td(on) VDD = - 4 V, RL = 4 Ω ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω 20 40 ns Rise Time tr 50 100 Turn-Off Delay Time td(off) 110 220 Fall Time tf 60 120 Source-Drain Reverse Recovery Time trr IF = - 1.7 A, dI/dt = 100 A/µs 60 100 |
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