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AD7682BCPZ Scheda tecnica(PDF) 10 Page - Analog Devices |
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AD7682BCPZ Scheda tecnica(HTML) 10 Page - Analog Devices |
10 / 32 page AD7682/AD7689 Data Sheet Rev. D | Page 10 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 VDD 2 REF NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. 3 REFIN 4 GND 5 GND 13 SCK 14 SDO 15 VIO 12 DIN 11 CNV TOP VIEW (Not to Scale) AD7682 Figure 4. AD7682 Pin Configuration PIN 1 INDICATOR 1 VDD 2 REF 3 REFIN 4 GND 5 GND 13 SCK 14 SDO 15 VIO 12 DIN 11 CNV TOP VIEW (Not to Scale) AD7689 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 5. AD7689 Pin Configuration Table 7. Pin Function Descriptions Pin No. AD7682 Mnemonic AD7689 Mnemonic Type1 Description 1, 20 VDD VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.6 V. 2 REF REF AI/O Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. 3 REFIN REFIN AI/O Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description. 4, 5 GND GND P Power Supply Ground. 6 NC IN4 AI AD7682: no connection. AD7689: Analog Input Channel 4. 7 IN2 IN5 AI AD7682: Analog Input Channel 2. AD7689: Analog Input Channel 5. 8 NC IN6 AI AD7682: no connection. AD7689: Analog Input Channel 6. 9 IN3 IN7 AI AD7682: Analog Input Channel 3. AD7689: Analog Input Channel 7. 10 COM COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common- mode point of 0 V or VREF/2 V. 11 CNV CNV DI Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled. 12 DIN DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. |
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