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AD590JCHIPS Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte AD590JCHIPS
Spiegazioni elettronici  2-Terminal IC Temperature Transducer
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD590JCHIPS Scheda tecnica(HTML) 6 Page - Analog Devices

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AD590
Data Sheet
Rev. G | Page 6 of 16
PRODUCT DESCRIPTION
The AD590 is a 2-terminal temperature-to-voltage transducer. It
is available in a variety of accuracy grades and packages. When
using the AD590 in die form, the chip substrate must be kept
electrically isolated (floating) for correct circuit operation.
Figure 6. Metallization Diagram
The AD590 uses a fundamental property of the silicon
transistors from which it is made to realize its temperature
proportional characteristic: if two identical transistors are
operated at a constant ratio of collector current densities, r,
then the difference in their base-emitter voltage is (kT/q)(In r).
Because both k (Boltzman’s constant) and q (the charge of an
electron) are constant, the resulting voltage is directly pro-
portional to absolute temperature (PTAT). (For a more detailed
description, see M.P. Timko, “A Two-Terminal IC Temperature
Transducer,” IEEE J. Solid State Circuits, Vol. SC-11, p. 784-788,
Dec. 1976. Understanding the Specifications–AD590.)
In the AD590, this PTAT voltage is converted to a PTAT current
by low temperature coefficient thin-film resistors. The total
current of the device is then forced to be a multiple of this
PTAT current. Figure 7 is the schematic diagram of the AD590.
In this figure, Q8 and Q11 are the transistors that produce the
PTAT voltage. R5 and R6 convert the voltage to current. Q10,
whose collector current tracks the collector currents in Q9 and
Q11, supplies all the bias and substrate leakage current for the
rest of the circuit, forcing the total current to be PTAT. R5 and
R6 are laser-trimmed on the wafer to calibrate the device at 25°C.
Figure 8 shows the typical V–I characteristic of the circuit at
25°C and the temperature extremes.
Figure 7. Schematic Diagram
Figure 8. V–I Plot
1725µM
1090µM
V–
V+
Q1
Q2
R2
1040Ω
Q5
Q3
Q4
C1
26pF
Q6
Q7
Q12
R4
11kΩ
Q8
Q10
Q9
CHIP
SUBSTRATE
Q11
1
1
8
R5
146Ω
R6
820Ω
R1
260Ω
+
R3
5kΩ
01
2
+150°C
423
298
218
+25°C
–55°C
34
SUPPLY VOLTAGE (V)
56
30


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