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74HCT00DB Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74HCT00DB Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 74HC_HCT00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 — 14 December 2011 7 of 16 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Load circuitry for measuring switching times 001aah768 tW tW tr tr tf VM VI negative pulse GND VI positive pulse GND 10 % 90 % 90 % 10 % VM VM VM tf VCC DUT RT VI VO CL G Table 9. Test data Type Input Load Test VI tr, tf CL 74HC00 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT00 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL |
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