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74LVT125DB Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74LVT125DB Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 16 page 74LVT_LVTH125_6 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 06 — 6 March 2006 4 of 16 Philips Semiconductors 74LVT125; 74LVTH125 3.3 V quad buffer; 3-state 6.2 Pin description 7. Functional description 7.1 Function table [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Table 3. Pin description Symbol Pin Description 1OE 1 1 output enable input (active LOW) 1A 2 1 data input 1Y 3 1 data output 2OE 4 2 output enable input (active LOW) 2A 5 2 data input 2Y 6 2 data output GND 7 ground (0 V) 3Y 8 3 data output 3A 9 3 data input 3OE 10 3 output enable input (active LOW) 4Y 11 4 data output 4A 12 4 data input 4OE 13 4 output enable input (active LOW) VCC 14 supply voltage Table 4. Function table[1] Control Input Output nOE nA nY LLL HH HX Z |
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