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AM8530H Scheda tecnica(PDF) 8 Page - Advanced Micro Devices

Il numero della parte AM8530H
Spiegazioni elettronici  Serial Communications Controller
Download  194 Pages
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Produttore elettronici  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM8530H Scheda tecnica(HTML) 8 Page - Advanced Micro Devices

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AMD
Table of Contents
6.3.1
Read Register 0 (Transmit/Receive Buffer
Status and External Status)
6–30
. . . . . . . . . . . . . . . . . . . .
6.3.2
Read Register 1
6–33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3
Read Register 2
6–35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4
Read Register 3
6–35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5
Read Register 6
6–36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6
Read Register 7
6–36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7
Read Register 8
6–37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.8
Read Register 10
6–37
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.9
Read Register 12
6–38
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.10 Read Register 13
6–38
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.11 Read Register 15
6–39
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 7
SCC Application Notes
7.1
Am8530H Initialization
7–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1
Introduction
7–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1.1 Register Overview
7–3
. . . . . . . . . . . . . . . . . . . .
7.1.1.2 Initialization Procedure
7–4
. . . . . . . . . . . . . . . .
7.1.1.3 Initialization Table Generation
7–6
. . . . . . . . . . .
7.1.1.4 Reset Conditions
7–6
. . . . . . . . . . . . . . . . . . . . .
7.2
Polled Asynchronous Mode
7–7
. . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1
Introduction
7–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2
SCC Interface
7–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3
SCC Initialization
7–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3.1 SCC Operating Mode Programming
7–9
. . . . . .
7.2.3.2 SCC Operating Mode Enables
7–10
. . . . . . . . . .
7.2.4
Transmit and Receive Routines
7–10
. . . . . . . . . . . . . . . . .
7.3
Interrupt Without Intack Asynchronous Mode
7–11
. . . . . . . . . . . .
7.3.1
Introduction
7–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2
SCC Interface
7–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3
SCC Initialization
7–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.1 SCC Operating Modes Programming
7–12
. . . . .
7.3.3.2 SCC Operating Mode Enables
7–13
. . . . . . . . . .
7.3.3.3 SCC Operating Mode Interrupts
7–13
. . . . . . . . .
7.3.4
Interrupt Routine
7–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4
Interfacing to the 8086/80186
7–15
. . . . . . . . . . . . . . . . . . . . . . . .
7.4.1
8086 (Also Called iAPX86) Overview
7–15
. . . . . . . . . . . .
7.4.1.1 The 8086 and Am8530H Interface
7–15
. . . . . . .
7.4.1.2 Initialization Routines
7–18
. . . . . . . . . . . . . . . . .
7.5
Interfacing to the 68000
7–20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
68000 Overview
7–20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2
The 68000 and Am8530H Without Interrupts
7–21
. . . . . .
7.5.3
The 68000 and Am8530H With Interrupts
7–23
. . . . . . . . .
7.5.4
The 68000 and Am8530H With Interrupts
via a PAL Device
7–25
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6
Am7960 and Am8530H Application
7–26
. . . . . . . . . . . . . . . . . . . .
7.6.1
Distributed Data Processing Overview
7–26
. . . . . . . . . . .
7.6.2
Data Communications at the Physical Layer
7–27
. . . . . . .
7.6.3
Hardware Considerations
7–28
. . . . . . . . . . . . . . . . . . . . .
7.6.4
Software Considerations
7–32
. . . . . . . . . . . . . . . . . . . . . .


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