Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

AM7992BDCB Scheda tecnica(PDF) 8 Page - Advanced Micro Devices

Il numero della parte AM7992BDCB
Spiegazioni elettronici  Serial Interface Adapter (SIA)
Download  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM7992BDCB Scheda tecnica(HTML) 8 Page - Advanced Micro Devices

Back Button AM7992BDCB Datasheet HTML 4Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 5Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 6Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 7Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 8Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 9Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 10Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 11Page - Advanced Micro Devices AM7992BDCB Datasheet HTML 12Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 27 page
background image
8
Am7992B
Input Signal Conditioning
The Carrier Receiver detects the presence of an in-
coming data packet by discerning and rejecting noise
from expected Manchester data. It also controls the
stop and start of the phase-locked loop during clock ac-
quisition. In the Am7992B, clock acquisition requires a
valid Manchester bit pattern of 1010 to lock on the in-
coming message (see Receive Timing—Start of Re-
ception Clock Acquisition waveform diagram).
Transient noise pulses less than 20 ns wide are re-
jected by the Carrier Receiver as noise and DC inputs
more positive than –175 mV are also suppressed. Car-
rier is detected for input signal wider than 45 ns with
amplitude more negative than –275 mV. When input
amplitude and pulse-width conditions are met at
Receive
±, RENA is asserted and a clock acquisition
cycle is initiated.
Clock Acquisition
When there is no activity at Receive
± (receiver is idle),
the receive oscillator is phase locked to TCLK. The first
negative clock transition (first valid Manchester “0”)
after RENA is asserted interrupts the receive oscillator
and presets the INTRCLK (internal clock) to the HIGH
state. The oscillator is then restarted at the second
Manchester “0” (bit time 4) and is phase locked to it. As
a result, the SIA acquires the clock from the incoming
Manchester bit stream in four bit times with a “1010”
Manchester bit pattern. The 10 MHz INTRCLK and
INTPLLCLK are derived from the internal oscillator,
which runs at four times the data rate (40.0 MHz). The
three clocks generated internally are utilized in the fol-
lowing manner:
s INTRCLK: After clock acquisition, INTRCLK
strobes the incoming data at 1/4 bit time. Receive
data path sets the input to the data decode register
(Figure 5).
s INTPLLCLK: At clock acquisition, INTPLLCLK is
phase locked to the incoming Manchester clock
transition at bit cell center (BCC). The transition at
BCC is compared to INTPLLCLK and phase correc-
tion is applied to maintain INTRCLK at 1/4 bit time
in the Manchester cell.
s INTCARR: From star t to end of a message,
INTCARR is active and establishes RENA turn-off
synchronously with RCLK rising edge. Internal car-
rier goes active when there is a negative transition
that is more negative than –275 mV and has a pulse
width greater or equal to 45 ns. Internal carrier goes
inactive typically 155 ns after the last positive tran-
sition at Receive
±.
When TEST is strapped LOW, RCLK and RX are en-
abled 1/4 bit time after clock acquisition in bit cell 5. RX
is at HIGH state when the receiver is idle and TEST is
strapped HIGH (no RLCK). RX, however, is undefined
when clock is acquired and may remain HIGH or
change to LOW state whenever RCLK is enabled. At
the 1/4 bit time of clock transition in bit cell 5, RCLK
makes its first external transition. It also strobes the in-
coming fifth bit Manchester “1.” RX may make a transi-
tion after the RCLK rising edge in bit cell 5, but its state
is still undefined. The Manchester “1” at bit 5 is clocked
to RX output at 1/4 bit time in bit cell 6.
PLL Tracking
After clock acquisition, the INTPLLCLK is compared to
the incoming transitions at BCC and the resulting
phase error is applied to a correction circuit. This circuit
ensures that INTPLLCLK remains locked on the re-
ceived signal. Individual bit cell phase corrections of
the V
CO are limited to 10% of the phase difference be-
tween BCC and INTPLLCLK. Hence, input data jitter is
reduced in RCLK by 10 to 1.
Carrier Tracking and End of Message
The carrier receiver monitors Receive
± input after
RENA is asserted for an end of message. INTCARR
deasserts typically 155 ns to 165 ns after the incoming
message transitions positive. This initiates the end of
reception cycle. INTCARR is strobed at 3/4 bit time by
the falling edge of INTRCLK. The time delay from the
03378I-9
Figure 5.
Receiver Section Detail
RX
RCLK
RENA
Q
D
Clock
Gating
DIV
40.0 MHz
V
CO
Phase
Detector
Noise
Reject
Filter
+
+
Carrier
REC
Data
REC


Codice articolo simile - AM7992BDCB

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Advanced Micro Devices
AM7996 AMD-AM7996 Datasheet
179Kb / 18P
   IEEE 802.3/Ethernet/Cheapernet Transceiver
AM7996DC AMD-AM7996DC Datasheet
179Kb / 18P
   IEEE 802.3/Ethernet/Cheapernet Transceiver
AM7996DCB AMD-AM7996DCB Datasheet
179Kb / 18P
   IEEE 802.3/Ethernet/Cheapernet Transceiver
AM7996DCTR AMD-AM7996DCTR Datasheet
179Kb / 18P
   IEEE 802.3/Ethernet/Cheapernet Transceiver
AM7996EVAL-HW AMD-AM7996EVAL-HW Datasheet
39Kb / 2P
   Ethernet/Cheapernet Transceiver Evaluation Kit
More results

Descrizione simile - AM7992BDCB

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
List of Unclassifed Man...
BT-120 ETC2-BT-120 Datasheet
113Kb / 6P
   serial adapter
logo
Microchip Technology
TC520A MICROCHIP-TC520A_13 Datasheet
208Kb / 16P
   Serial Interface Adapter for TC500 A/D Converter Family
2001-2012 11/29/12
TC520A MICROCHIP-TC520A Datasheet
453Kb / 16P
   Serial Interface Adapter for TC500 A/D Converter Family
2002
logo
TelCom Semiconductor, I...
TC520A TELCOM-TC520A Datasheet
81Kb / 8P
   SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY
logo
Texas Instruments
USB2ANY TI1-USB2ANY Datasheet
655Kb / 21P
[Old version datasheet]   Interface Adapter
logo
IK Semicon Co., Ltd
IK2102DW IKSEMICON-IK2102DW Datasheet
2Mb / 23P
   Serial Interface
IK2108DW IKSEMICON-IK2108DW Datasheet
547Kb / 21P
   Serial Interface
logo
List of Unclassifed Man...
SD200 ETC-SD200 Datasheet
536Kb / 2P
   Bluetooth-serial adapter
SD1100 ETC-SD1100 Datasheet
190Kb / 2P
   Bluetooth-serial adapter
ZS10 ETC-ZS10 Datasheet
443Kb / 2P
   Zigbe serial adapter
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com