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AM7992BDCB Scheda tecnica(PDF) 8 Page - Advanced Micro Devices |
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AM7992BDCB Scheda tecnica(HTML) 8 Page - Advanced Micro Devices |
8 / 27 page 8 Am7992B Input Signal Conditioning The Carrier Receiver detects the presence of an in- coming data packet by discerning and rejecting noise from expected Manchester data. It also controls the stop and start of the phase-locked loop during clock ac- quisition. In the Am7992B, clock acquisition requires a valid Manchester bit pattern of 1010 to lock on the in- coming message (see Receive Timing—Start of Re- ception Clock Acquisition waveform diagram). Transient noise pulses less than 20 ns wide are re- jected by the Carrier Receiver as noise and DC inputs more positive than –175 mV are also suppressed. Car- rier is detected for input signal wider than 45 ns with amplitude more negative than –275 mV. When input amplitude and pulse-width conditions are met at Receive ±, RENA is asserted and a clock acquisition cycle is initiated. Clock Acquisition When there is no activity at Receive ± (receiver is idle), the receive oscillator is phase locked to TCLK. The first negative clock transition (first valid Manchester “0”) after RENA is asserted interrupts the receive oscillator and presets the INTRCLK (internal clock) to the HIGH state. The oscillator is then restarted at the second Manchester “0” (bit time 4) and is phase locked to it. As a result, the SIA acquires the clock from the incoming Manchester bit stream in four bit times with a “1010” Manchester bit pattern. The 10 MHz INTRCLK and INTPLLCLK are derived from the internal oscillator, which runs at four times the data rate (40.0 MHz). The three clocks generated internally are utilized in the fol- lowing manner: s INTRCLK: After clock acquisition, INTRCLK strobes the incoming data at 1/4 bit time. Receive data path sets the input to the data decode register (Figure 5). s INTPLLCLK: At clock acquisition, INTPLLCLK is phase locked to the incoming Manchester clock transition at bit cell center (BCC). The transition at BCC is compared to INTPLLCLK and phase correc- tion is applied to maintain INTRCLK at 1/4 bit time in the Manchester cell. s INTCARR: From star t to end of a message, INTCARR is active and establishes RENA turn-off synchronously with RCLK rising edge. Internal car- rier goes active when there is a negative transition that is more negative than –275 mV and has a pulse width greater or equal to 45 ns. Internal carrier goes inactive typically 155 ns after the last positive tran- sition at Receive ±. When TEST is strapped LOW, RCLK and RX are en- abled 1/4 bit time after clock acquisition in bit cell 5. RX is at HIGH state when the receiver is idle and TEST is strapped HIGH (no RLCK). RX, however, is undefined when clock is acquired and may remain HIGH or change to LOW state whenever RCLK is enabled. At the 1/4 bit time of clock transition in bit cell 5, RCLK makes its first external transition. It also strobes the in- coming fifth bit Manchester “1.” RX may make a transi- tion after the RCLK rising edge in bit cell 5, but its state is still undefined. The Manchester “1” at bit 5 is clocked to RX output at 1/4 bit time in bit cell 6. PLL Tracking After clock acquisition, the INTPLLCLK is compared to the incoming transitions at BCC and the resulting phase error is applied to a correction circuit. This circuit ensures that INTPLLCLK remains locked on the re- ceived signal. Individual bit cell phase corrections of the V CO are limited to 10% of the phase difference be- tween BCC and INTPLLCLK. Hence, input data jitter is reduced in RCLK by 10 to 1. Carrier Tracking and End of Message The carrier receiver monitors Receive ± input after RENA is asserted for an end of message. INTCARR deasserts typically 155 ns to 165 ns after the incoming message transitions positive. This initiates the end of reception cycle. INTCARR is strobed at 3/4 bit time by the falling edge of INTRCLK. The time delay from the 03378I-9 Figure 5. Receiver Section Detail RX RCLK RENA Q D Clock Gating DIV 40.0 MHz V CO Phase Detector Noise Reject Filter + – + Carrier REC Data REC |
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