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FAN6754BMRMY Scheda tecnica(PDF) 11 Page - Fairchild Semiconductor |
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FAN6754BMRMY Scheda tecnica(HTML) 11 Page - Fairchild Semiconductor |
11 / 24 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6921AMR • Rev. 1.0.2 11 Electrical Characteristics (Continued) VDD=15V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit VCTL-PFC-OFF Threshold Voltage on FB Pin for PFC EnableDisable RANGE Pin Internally Open 1.80 1.85 1.90 V RANGE Pin Internally Ground 1.75 1.80 1.85 VCTL-PFC-ON Threshold Voltage on FB Pin for PFC Disable Enable RANGE Pin Internally Open 1.90 1.95 2.00 V RANGE Pin Internally Ground 1.80 1.85 1.90 tPFC-OFF PFC Disable Debounce Time PFC Enable Disable 400 500 600 ms tPFC-ON PFC Enable Debounce Time PFC Disable Enable 2.0 2.5 3.0 ms tSTARTER-PWM Start Timer (Time-Out Timer) VFB <VG 1.85 2.25 2.65 ms VFB >VFB-OLP 22 28 34 µs PWM Output Section VCLAMP PWM Gate Output Clamping Voltage VDD=25 V 16.0 17.5 19.0 V VOL PWM Gate Output Voltage Low VDD=15 V, IO=100 mA 1.5 V VOH PWM Gate Output Voltage High VDD=15 V, IO=100 mA 8 V tR PWM Gate Output Rising Time CL=3 nF, VDD=12 V, 20~80% 80 110 ns tF PWM Gate Output Falling Time CL=3 nF, VDD=12 V, 20~80% 40 70 ns Current Sense Section tPD Delay to Output 150 200 ns VLIMIT Limit Voltage on CSPWM Pin for Over-Power Compensation IDET <75 µA, TA=25°C 0.81 0.84 0.87 V IDET=185 µA, TA=25°C 0.69 0.72 0.75 IDET=350 µA, TA=25°C 0.55 0.58 0.61 IDET=550 µA, TA=25°C 0.37 0.40 0.43 VSLOPE Slope Compensation (4) tON=45 µs, RANGE=Open 0.25 0.30 0.35 V tON=0 µs 0.05 0.10 0.15 tON-BNK Leading-Edge Blanking Time 300 ns VCS-FLOATING CSPWM Pin Floating VCSPWM Clamped High Voltage CSPWM Pin Floating 4.5 5.0 V tCS-H Delay with CSPWM Pin Floating CSPWM Pin Floating 150 µs Continued on the fo llowing page… |
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