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AM27C020-200DE5B Scheda tecnica(PDF) 5 Page - Advanced Micro Devices |
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AM27C020-200DE5B Scheda tecnica(HTML) 5 Page - Advanced Micro Devices |
5 / 12 page Am27C020 5 FUNCTIONAL DESCRIPTION Device Erasure In order to clear all locations of their programmed con- tents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be ob- tained by exposure to an ultraviolet lamp—wavelength of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be re- moved from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 Å, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, ex- posure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance. Device Programming Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the device through the programming pro- cedure. The device enters the programming mode when 12.75 V ± 0.25 V is applied to the V PP pin, and CE# and PGM# are at VIL and OE# is at VIH. For programming, the data to be programmed is ap- plied 8 bits in parallel to the data pins. The flowchar t in the Programming section of the EPROM Products Data Book (Section 5, Figure 5-1) shows AMD’s Flashrite algorithm. The Flashrite algo- rithm reduces programming time by using a 100 µs pro- gramming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that ad- dress is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while se- quencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 5 of the EPROM Products Data Book for additional programming information and spec- ifications. Program Inhibit Programming different data to multiple devices in par- allel is easily accomplished. Except for CE#, all like in- puts of the devices may be common. A TTL low-level program pulse applied to one device’s CE# input with VPP = 12.75 V ± 0.25 V and PGM# LOW, and OE# HIGH will program that particular device. A high-level CE# input inhibits the other devices from being pro- grammed. Program Verify A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# and CE#, at VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V. Autoselect Mode The autoselect mode provides manufacturer and de- vice identification through identifier codes on DQ0– DQ7. This mode is primarily intended for programming equipment to automatically match a device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25 °C ± 5°C ambient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by tog- gling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit. Read Mode To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# con- trols the power to the device and is typically used to se- lect the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACC–tOE. Refer to the Switching Waveforms section for the timing diagram. Standby Mode The device enters the CMOS standby mode when CE# is at VCC ± 0.3 V. Maximum VCC current is reduced to 100 µA. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, indepen- dent of the OE# input. Output OR-Tieing To accommodate multiple memory connections, a two-line control function provides: s Low memory power dissipation, and s Assurance that output bus contention will not occur. |
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