AM29BDS323D datasheet(7/44 Pages) AMD

Il numero della parte	AM29BDS323D

Spiegazioni elettronici	32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

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Produttore elettronici	AMD [Advanced Micro Devices]

Homepage	http://www.amd.com

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Am29BDS323D

7

P R E L I M INARY

INPUT/OUTPUT DESCRIPTIONS

A16–A20

=

Address Inputs

A/DQ0–

=

Multiplexed Address/Data input/output

A/DQ15

CE#

=

Chip Enable Input. Asynchronous

relative to CLK for the Burst mode.

OE#

=

Output Enable Input. Asynchronous

relative to CLK for the Burst mode.

WE#

=

Write Enable Input.

VCC

=

Device Power Supply (1.7 V–1.9 V).

VSS

=

Ground

NC

=

No Connect; not connected internally

RDY

=

Ready output; indicates the status of

the Burst read. Low = data not valid at

expected time. High = data valid.

CLK

=

The first rising edge of CLK in

conjunction with AVD# low latches

address input and activates burst

mode operation. After the initial word

is output, subsequent rising edges of

CLK increment the internal address

counter. CLK should remain low

during asynchronous access.

AVD#

=

Address Valid input. Indicates to

device that the valid address is

present on the address inputs

(address bits A0–A15 are multiplexed,

address bits A16–A20 are address

only).

Low = for asynchronous mode,

indicates valid address; for burst

mode, causes starting address to be

latched on rising edge of CLK.

High = device ignores address inputs

PS

=

Power Saving input/output

During a read operation, PS indicates

whether or not the data on the outputs

are inverted. Low = data not inverted;

High = data inverted

RESET#

=

Hardware reset input. Low = device

resets and returns to reading array

data. RESET# must be low during

device power up.

WP#

=

Hardware write protect input. Low =

disables writes to SA70 and SA71

VPP

=

At 12 V, accelerates programming;

automatically places device in unlock

bypass mode. At VIL, disables

program and erase functions. Should

be at VIH for all other conditions.

LOGIC SYMBOL

5

16

A/DQ0–

A/DQ15

A16–A20

CE#

OE#

WE#

RESET#

CLK

RDY

PS

AVD#

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